公开(公告)号：US20180358983A1

公开(公告)日：2018-12-13

申请号：US15803073

申请日：2017-11-03

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hyuk KIM ,  Insan JEON

IPC: H03M13/11

CPC classification number: H03M13/1125 ,  G06F17/13 ,  H03M13/1108 ,  H03M13/1134 ,  H03M13/114

Abstract: Provided is a low density parity check (LDPC) decoder. An LDPC decoder according to an embodiment of the inventive concept includes a variable node calculator for adding an input log-likelihood ratio (LLR) to message information of a check node to output the added values, a check node calculator for extracting signs of the output values of the variable node calculator, determining a minimum value of the output values, and calculating a correction term for the output values by using a binary logarithm to transmit to the variable node calculator, a hard decision block for determining bit values of the output values of the variable node calculator, and a parity check block for performing a parity check operation for determining validity of the bit value.