公开(公告)号：US12095481B2

公开(公告)日：2024-09-17

申请号：US17586290

申请日：2022-01-27

申请人： Kioxia Corporation

发明人： Avi Steiner ,  Zion Nahisi ,  Ofir Kanter ,  Amir Nassie ,  Hanan Weingarten

IPC分类号： H03M13/29 ,  H03M13/11 ,  H03M13/15 ,  H03M13/45

CPC分类号： H03M13/2909 ,  H03M13/1108 ,  H03M13/1125 ,  H03M13/1128 ,  H03M13/152 ,  H03M13/458

摘要： A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.

公开(公告)号：US20240080045A1

公开(公告)日：2024-03-07

申请号：US18271134

申请日：2021-01-08

申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION

发明人： Takeshi KAKIZAKI ,  Masanori NAKAMURA ,  Fukutaro HAMAOKA

IPC分类号： H03M13/11 ,  H03M13/29

CPC分类号： H03M13/1125 ,  H03M13/2978

摘要： There is provided an encoding circuit used for coherent digital signal processing, including: a serial-parallel circuit that divides input data into a plurality of pieces of divided data by serial-parallel conversion; a plurality of encoders that adds an error correction code to the divided data and encodes the divided data; and a bit conversion circuit that converts a bit sequence in order to make an amount of noise generated by a communication channel non-uniform among the plurality of pieces of divided data encoded by each of the plurality of encoders.

公开(公告)号：US11736122B1

公开(公告)日：2023-08-22

申请号：US17654545

申请日：2022-03-11

申请人： International Business Machines Corporation

发明人： Theodore James Yoder

IPC分类号： H03M13/11 ,  H03M13/01 ,  H03M13/09

CPC分类号： H03M13/1125 ,  H03M13/01 ,  H03M13/09

摘要： Techniques regarding quantum error correction are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a maximum-likelihood decoder component that executes a maximum-likelihood decoding algorithm to determine an error correction based on a decoding hypergraph that characterizes error-sensitive events associated with a quantum error-correcting code executed on a quantum circuit.

公开(公告)号：US11652566B2

公开(公告)日：2023-05-16

申请号：US16603623

申请日：2018-07-30

申请人： Ciena Corporation

发明人： Shahab Oveis Gharan ,  Mohammad Ehsan Seifi ,  Kim B. Roberts

IPC分类号： H04L1/00 ,  H03M13/25 ,  H03M13/29 ,  H03M13/11 ,  H04L1/20 ,  H03M13/03 ,  G06F17/18 ,  G06F17/15

CPC分类号： H04L1/00 ,  G06F17/18 ,  H03M13/03 ,  H03M13/1125 ,  H03M13/253 ,  H03M13/29 ,  H03M13/2948 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0063 ,  H04L1/0064 ,  H04L1/0066 ,  H04L1/203 ,  G06F17/156

摘要： In data communications, a suitably designed contrast coding scheme, comprising a process of contrast encoding (108) at a transmitter end (101) and a process of contrast decoding (120) at a receiver end (103), may be used to create contrast between the bit error rates ‘BERs’ experienced by different classes of bits. Contrast coding may be used to tune the BERs experienced by different subsets of bits, relative to each other, to better match a plurality of forward error correction ‘FEC’ schemes (104, 124) used for transmission of information bits (102), which may ultimately provide a communications system (100) having a higher noise tolerance, or greater data capacity, or smaller size, or lower heat.

公开(公告)号：US20190245560A1

公开(公告)日：2019-08-08

申请号：US16267007

申请日：2019-02-04

申请人： QUALCOMM Incorporated

发明人： Wei Yang ,  Ying Wang ,  Jing Jiang ,  Yang Yang ,  Gabi Sarkis

IPC分类号： H03M13/13 ,  H03M13/00 ,  H03M13/11 ,  H04L1/00

CPC分类号： H03M13/13 ,  H03M13/005 ,  H03M13/033 ,  H03M13/1125 ,  H03M13/1137 ,  H03M13/6362 ,  H04L1/0057 ,  H04L1/0068

摘要： Methods, systems, and devices for wireless communications are described. An encoder of a wireless device may receive a number of information bits and a block size for transmission. If the block size is not a power of two, the encoder may round the block size up to the nearest power of 2, generate a larger codeword, and puncture the excess bits. The punctured bits may affect a rate of polarization when generating a polar code, and sub-blocks with a high number of punctured bits may produce too few sufficiently polarized channels. The encoder may implement a capacity backoff when polar coding to identify a greater number of polarized channels. The encoder may assign information bits to sufficiently polarized channels of the greater number of polarized channels.

公开(公告)号：US20190140660A1

公开(公告)日：2019-05-09

申请号：US16242155

申请日：2019-01-08

申请人： Intel Corporation

发明人： Poovaiah M. PALANGAPPA ,  Ravi H. MOTWANI ,  Santhosh K. VANAPARTHY

IPC分类号： H03M13/11 ,  G06F11/10 ,  G11C29/04

CPC分类号： H03M13/1125 ,  G06F11/1012 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/04 ,  G11C2029/0411 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/3723 ,  H03M13/6325 ,  H03M13/658

摘要： Examples include techniques for improving low-density parity check decoder performance for a binary asymmetric channel in a multi-die scenario. Examples include logic for execution by circuity to decode an encoded codeword of data received from a memory having a plurality of dies, bits of the encoded codeword stored across the plurality of dies, using predetermined log-likelihood ratios (LLRs) to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the predetermined LLRs when the decoded codeword is not correct, up to a first number of times when the decoded codeword is not correct. When a correct decoded codeword is not produced using predetermined LLRs, further logic may be executed to estimate the LLRs for a plurality of buckets of the plurality of dies, normalize magnitudes of the estimated LLRs, decode the encoded codeword using the normalized estimated LLRs to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the normalized estimated LLRs when the decoded codeword is not correct, up to a second number of times when the decoded codeword is not correct.

公开(公告)号：US20170366200A1

公开(公告)日：2017-12-21

申请号：US15692679

申请日：2017-08-31

申请人： PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA

发明人： Yutaka Murakami ,  Shutai Okamura

IPC分类号： H03M13/11 ,  H03M13/00 ,  H03M13/15 ,  H04L1/00

CPC分类号： H03M13/116 ,  H03M13/005 ,  H03M13/1125 ,  H03M13/15 ,  H03M13/616 ,  H03M13/6362 ,  H03M13/6527 ,  H04L1/0041

摘要： Disclosed are an encoder, a transmitting device, a coding method and a transmission method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block coding is used. A puncture pattern setting unit searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code.

公开(公告)号：US20170279560A1

公开(公告)日：2017-09-28

申请号：US15618404

申请日：2017-06-09

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： YUTAKA MURAKAMI ,  TOMOHIRO KIMURA ,  MIKIHIRO OUCHI

IPC分类号： H04L1/00 ,  H03M13/11

CPC分类号： H04L1/0054 ,  H03M13/1111 ,  H03M13/1125 ,  H03M13/3707 ,  H03M13/3715 ,  H03M13/373 ,  H03M13/3776 ,  H03M13/616 ,  H04L1/005 ,  H04L1/0053 ,  H04L1/0057 ,  H04L1/0061 ,  H04L2001/0097

摘要： A decoding device includes: a BP decoder that performs BP decoding on an input signal: a maximum likelihood decoder that performs maximum likelihood decoding on a signal subjected to the BP decoding; and a selector that selects one of the input signal, the signal subjected to the BP decoding, and a signal subjected to the maximum likelihood decoding. In a configuration of the decoding device, when a decoder is appropriately operated according to quality of data, a calculation scale can be reduced, and power consumption can be decreased.

公开(公告)号：US20170264316A1

公开(公告)日：2017-09-14

申请号：US15456315

申请日：2017-03-10

申请人： Samsung Electronics Co., Ltd. ,  KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION

发明人： Myeong-Woo Lee ,  Young-Kil Suh ,  Jun Heo ,  Jong-Hyun Baik

IPC分类号： H03M13/11 ,  H04L1/20 ,  H04L1/00

CPC分类号： H03M13/1125 ,  H04L1/0051 ,  H04L1/0053 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/20

摘要： The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as a long term evolution (LTE). A method of a receiving apparatus in a communication system supporting a low density parity check (LDPC) code is provided. The method includes deactivating variable nodes of which absolute values of log likelihood ratio (LLR) values are greater than or equal to a first threshold value; changing LLR values of variable nodes of which absolute values of LLR values are less than a second threshold value among variable nodes other than the deactivated variable nodes to a preset value, and detecting LLR values of check nodes based on LLR values of the variable nodes other than the deactivated variable nodes.

公开(公告)号：US09672103B2

公开(公告)日：2017-06-06

申请号：US14847576

申请日：2015-09-08

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Yoshifumi Nishi ,  Takao Marukame ,  Yuichiro Mitani

IPC分类号： H03M13/03 ,  G06F11/10 ,  H03M13/11 ,  H03M13/00

CPC分类号： G06F11/1068 ,  H03M13/1125 ,  H03M13/6597

摘要： According to an embodiment, a decoding device includes a check node processor, and a converter. The probability acquirer is configured to acquire. The check node processor is configured to perform check node processing during in a decoding operation of encoded data. A probability value for each bit of the encoded data is treated as an initial variable node in the check node processing. The converter is configured to convert, into bit values, updated values of the probability values based on the check node processing. The check node processor includes a check node circuit having a topology corresponding to a two-state trellis diagram representing the check node processing. The check node circuit includes conducting wires each corresponding to an edge of the two-state trellis diagram and includes switch units which are arranged on the conducting wires and switching of which is controlled according to a predetermined probability.