公开(公告)号：US20040199802A1

公开(公告)日：2004-10-07

申请号：US10455372

申请日：2003-06-06

Applicant: Faraday Technology Corp.

Inventor： Chih-Wen Lin

IPC: G06F001/12

CPC classification number: G06F1/12 ,  H03L7/16

Abstract: A higher frequency clock and a lower frequency clock are locked at a predetermined phase relationship. A total number of pulses of the higher frequency clock occurring between two sequential rising edges of the lower frequency are calculated. A count start signal is generated in response to a rising edge of the lower frequency clock. A value of a lower frequency clock count is set in response to the count start signal. The value of the lower frequency clock decrements in accordance with a frequency of the higher frequency clock. When the value of the lower frequency clock has decreased by the total number of pulses of the higher frequency clock occurring between two consecutive rising edges of the lower frequency minus 1, a synchronization signal is generated for indicating occurrence of the predetermined phase relationship between the higher frequency clock and the lower frequency clock.

Abstract translation: 较高频率时钟和较低频率时钟被锁定在预定的相位关系。 计算在较低频率的两个连续上升沿之间出现的较高频率时钟的总脉冲数。 响应于较低频率时钟的上升沿产生计数开始信号。 响应于计数开始信号设置较低频率时钟计数的值。 较低频率时钟的值根据较高频率时钟的频率递减。 当较低频率时钟的值减小了在较低频率的两个连续上升沿之间出现的较高频率时钟的总脉冲数减1时，产生同步信号以指示较高频率时钟之间的预定相位关系的出现 频率时钟和较低频率时钟。