公开(公告)号：US20190214348A1

公开(公告)日：2019-07-11

申请号：US15867118

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wen Liu ,  Sebastian T. Ventrone ,  Adam C. Smith ,  Janice M. Adams ,  Nazmul Habib

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/66

Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

公开(公告)号：US10700013B2

公开(公告)日：2020-06-30

申请号：US15867118

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wen Liu ,  Sebastian T. Ventrone ,  Adam C. Smith ,  Janice M. Adams ,  Nazmul Habib

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528

Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.