公开(公告)号：US20180138209A1

公开(公告)日：2018-05-17

申请号：US15351678

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wen Liu ,  Criag M. Bocash ,  Carole D. Graas ,  Fen Chen

IPC: H01L27/12 ,  H01L23/373 ,  H01L21/3115 ,  H01L21/762

CPC classification number: H01L27/1211 ,  H01L21/02002 ,  H01L21/76251 ,  H01L21/76256 ,  H01L27/1203

Abstract: An SOI substrate includes a metallic doped isolation (i.e., buried oxide) layer. Doping of the isolation layer increases its thermal conductivity, which improves heat conduction and decreases the susceptibility of devices formed on the substrate to temperature-induced deterioration and/or failure over time. The amount as well as the configuration of the doping can be tailored to specific circuit architectures.

公开(公告)号：US20190214348A1

公开(公告)日：2019-07-11

申请号：US15867118

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wen Liu ,  Sebastian T. Ventrone ,  Adam C. Smith ,  Janice M. Adams ,  Nazmul Habib

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/66

Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

公开(公告)号：US10700013B2

公开(公告)日：2020-06-30

申请号：US15867118

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wen Liu ,  Sebastian T. Ventrone ,  Adam C. Smith ,  Janice M. Adams ,  Nazmul Habib

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528

Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.