公开(公告)号：US10365328B2

公开(公告)日：2019-07-30

申请号：US15636793

申请日：2017-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jian Sun ,  Chao Meng ,  Xiaoxiao Li ,  Yinpeng Lu

IPC: G01R31/00 ,  G01R31/3185 ,  G11C29/30 ,  G06F11/22 ,  H03K19/177 ,  H03K19/173 ,  G11C29/12 ,  G11C29/32

Abstract: A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal.