公开(公告)号：US20140227845A1

公开(公告)日：2014-08-14

申请号：US13766922

申请日：2013-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanxiang Liu ,  Manfred Eller ,  Johannes van Meer

IPC: H01L21/8234

CPC classification number: H01L21/823412 ,  H01L21/823418

Abstract: One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second N-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material. In some cases, the capping material layer may be formed of a material having a Young's modulus of at least 180 GPa.

Abstract translation: 本文公开的一种说明性方法涉及形成由分别形成在第一和第二活性区域中和第二活性区域上的第一和第二N型晶体管组成的集成电路产品。 该方法通常涉及对第一和第二有源区域执行公共阈值电压调整离子注入工艺，形成第一和第二晶体管，执行非晶离子注入工艺以在第一有源区域中选择性地形成非晶材料区域，但不在第 第二有源区，在执行非晶化离子注入工艺之后，在第一和第二晶体管上方形成覆盖材料层，并执行重结晶退火工艺，以将非晶材料区域的至少一部分转化为结晶材料。 在一些情况下，封盖材料层可以由杨氏模量为至少180GPa的材料形成。

公开(公告)号：US08846476B2

公开(公告)日：2014-09-30

申请号：US13766922

申请日：2013-02-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Manfred Eller ,  Johannes van Meer

IPC: H01L21/8236 ,  H01L21/336 ,  H01L21/8234

CPC classification number: H01L21/823412 ,  H01L21/823418

Abstract: One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second N-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material. In some cases, the capping material layer may be formed of a material having a Young's modulus of at least 180 GPa.

Abstract translation: 本文公开的一种说明性方法涉及形成由分别形成在第一和第二活性区域中和第二活性区域上的第一和第二N型晶体管组成的集成电路产品。 该方法通常涉及对第一和第二有源区域执行公共阈值电压调整离子注入过程，形成第一和第二晶体管，执行非晶离子注入工艺，以在第一有源区域中选择性地形成非晶材料区域，但不在第 第二有源区，在执行非晶化离子注入工艺之后，在第一和第二晶体管上方形成覆盖材料层，并执行重结晶退火工艺，以将非晶材料区域的至少一部分转化为结晶材料。 在一些情况下，封盖材料层可以由杨氏模量为至少180GPa的材料形成。