公开(公告)号：US09490257B2

公开(公告)日：2016-11-08

申请号：US14574460

申请日：2014-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Norbert Arnold

IPC: H01L21/02 ,  H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10829 ,  H01L27/10867 ,  H01L27/1203 ,  H01L28/90 ,  H01L29/945

Abstract: After forming a recessed conductive material portion over a deep trench capacitor located in a lower portion of a deep trench embedded in a substrate, a hard mask layer is formed over a top semiconductor layer of the substrate and the recessed conductive material portion such that the hard mask layer completely fills the deep trench. Next, the hard mask layer, the top semiconductor layer and the recessed conductive material portion are patterned to form a laterally contacting pair of a semiconductor fin and a conductive strap structure over the deep trench capacitor as well as a dielectric cap embedded in the deep trench. The dielectric cap vertically contacts a lower portion of the conductive strap structure and laterally surrounds a portion of an upper portion of the conductive strap structure that is not in contact with the semiconductor fin.

Abstract translation: 在位于埋入基板的深沟槽的下部的深沟槽电容器上形成凹陷的导电材料部分之后，在衬底的顶部半导体层和凹入的导电材料部分之上形成硬掩模层，使得硬的 掩模层完全填满深沟。 接下来，对硬掩模层，顶部半导体层和凹入的导电材料部分进行图案化以在深沟槽电容器上形成横向接触的一对半导体鳍片和导电带结构，以及嵌入深沟槽中的电介质盖 。 电介质盖垂直地接触导电带结构的下部，并且横向地围绕导电带结构的不与半导体鳍接触的上部的一部分。

公开(公告)号：US20160181252A1

公开(公告)日：2016-06-23

申请号：US14574460

申请日：2014-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Norbert Arnold

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10829 ,  H01L27/10867 ,  H01L27/1203 ,  H01L28/90 ,  H01L29/945

Abstract: After forming a recessed conductive material portion over a deep trench capacitor located in a lower portion of a deep trench embedded in a substrate, a hard mask layer is formed over a top semiconductor layer of the substrate and the recessed conductive material portion such that the hard mask layer completely fills the deep trench. Next, the hard mask layer, the top semiconductor layer and the recessed conductive material portion are patterned to form a laterally contacting pair of a semiconductor fin and a conductive strap structure over the deep trench capacitor as well as a dielectric cap embedded in the deep trench. The dielectric cap vertically contacts a lower portion of the conductive strap structure and laterally surrounds a portion of an upper portion of the conductive strap structure that is not in contact with the semiconductor fin.

Abstract translation: 在位于埋入基板的深沟槽的下部的深沟槽电容器上形成凹陷的导电材料部分之后，在衬底的顶部半导体层和凹入的导电材料部分之上形成硬掩模层，使得硬的 掩模层完全填满深沟。 接下来，对硬掩模层，顶部半导体层和凹入的导电材料部分进行图案化以在深沟槽电容器上形成半导体鳍片和导电带结构的横向接触的一对以及嵌入深沟槽中的电介质盖 。 电介质盖垂直地接触导电带结构的下部，并且横向地围绕导电带结构的不与半导体鳍接触的上部的一部分。

公开(公告)号：US09293382B2

公开(公告)日：2016-03-22

申请号：US14522626

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Norbert Arnold ,  Jin Liu ,  Brian W. Messenger ,  Oliver D. Patterson

IPC: H01L23/58 ,  H01L27/12 ,  G01R31/26 ,  H01L21/20 ,  H01L21/66 ,  H01L49/02 ,  H01L21/84 ,  H01L29/66 ,  H01L27/108 ,  H01L21/762

CPC classification number: H01L22/14 ,  H01L21/762 ,  H01L21/84 ,  H01L22/32 ,  H01L22/34 ,  H01L27/10861 ,  H01L27/10894 ,  H01L27/1203 ,  H01L28/40 ,  H01L28/60 ,  H01L29/66181

Abstract: A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure.