公开(公告)号：US20180197734A1

公开(公告)日：2018-07-12

申请号：US15405026

申请日：2017-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bhupesh CHANDRA ,  Annie LEVESQUE ,  Matthew W. STOKER ,  Shreesh NARASIMHA ,  Viorel ONTALUS ,  Michael STEIGERWALT ,  Joshua BELL

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/7848

Abstract: Reducing wormhole formation during n-type transistor fabrication includes providing a starting structure, the starting structure including a semiconductor substrate, a n-type source region and a n-type drain region of a transistor. The method further includes removing a portion of each of the n-type source region and the n-type drain region, the removing creating a source trench and a drain trench, and forming a buffer layer of silicon-based material(s) over the n-type source region and n-type drain region that is sufficiently thick to inhibit interaction between metal contaminants that may be present below surfaces of the n-type source trench and/or the n-type drain trench, and halogens subsequently introduced prior to source and drain formation. A resulting semiconductor structure is also provided.

公开(公告)号：US20200066593A1

公开(公告)日：2020-02-27

申请号：US16109258

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Annie LEVESQUE ,  Qun GAO ,  Hui ZANG ,  Rishikesh KRISHNAN ,  Bharat KRISHNAN ,  Curtis DURFEE

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535 ,  H01L21/02 ,  H01L29/40

Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.

公开(公告)号：US20190326112A1

公开(公告)日：2019-10-24

申请号：US15957491

申请日：2018-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shahab SIDDIQUI ,  Hamed PARVANEH ,  Mira PARK ,  Annie LEVESQUE ,  Yinxiao YANG ,  Hongyi MI ,  Asli SIRMAN

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/311

Abstract: A method of cleaning a low-k spacer cavity by a low energy RF plasma at a specific substrate temperature for a defect free epitaxial growth of Si, SiGe, Ge, III-V and III-N and the resulting device are provided. Embodiments include providing a substrate with a low-k spacer cavity; cleaning the low-k spacer cavity with a low energy RF plasma at a substrate temperature between room temperature to 600° C.; and forming an epitaxy film or a RSD in the low-k spacer cavity subsequent to the low energy RF plasma cleaning.