公开(公告)号：US10699973B2

公开(公告)日：2020-06-30

申请号：US15804165

申请日：2017-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Patrick S. Spinney ,  Jeffrey C. Stamm

IPC: H01L23/544 ,  H01L23/00 ,  H01L21/66 ,  H01L21/78

Abstract: A test structure for semiconductor chips of a wafer, and the method of forming the same is included. The test structure may include a first portion disposed within a corner area of a first chip on the wafer, and at least another portion disposed within another corner of another chip on the wafer, wherein before dicing of the chips, the portions form the test structure. The test structure may include an electronic test structure or an optical test structure. The electronic test structure may include probe pads, each probe pad positioned across two or more corner areas of two or more chips. The corner areas including the test structures disposed therein may be removed from the chips during a dicing of the chips.

公开(公告)号：US20190139841A1

公开(公告)日：2019-05-09

申请号：US15804165

申请日：2017-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Patrick S. Spinney ,  Jeffrey C. Stamm

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/544 ,  H01L21/78

Abstract: A test structure for semiconductor chips of a wafer, and the method of forming the same is included. The test structure may include a first portion disposed within a corner area of a first chip on the wafer, and at least another portion disposed within another corner of another chip on the wafer, wherein before dicing of the chips, the portions form the test structure. The test structure may include an electronic test structure or an optical test structure. The electronic test structure may include probe pads, each probe pad positioned across two or more corner areas of two or more chips. The corner areas including the test structures disposed therein may be removed from the chips during a dicing of the chips.