公开(公告)号：US20210074577A1

公开(公告)日：2021-03-11

申请号：US17086925

申请日：2020-11-02

申请人： GLOBALFOUNDRIES Inc.

发明人： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC分类号： H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/74 ,  H01L29/32

摘要： Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US10910304B2

公开(公告)日：2021-02-02

申请号：US16256595

申请日：2019-01-24

申请人： GLOBALFOUNDRIES INC.

发明人： Anthony K. Stamper ,  Daisy A. Vaughn ,  Stephen R. Bosley ,  Zhong-Xiang He

IPC分类号： H01L23/522 ,  H01L27/08 ,  H01L49/02 ,  H01G4/33 ,  H01G4/08 ,  H01G4/232 ,  H01L23/528

摘要： The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.

公开(公告)号：US10903316B2

公开(公告)日：2021-01-26

申请号：US16575675

申请日：2019-09-19

申请人： GLOBALFOUNDRIES INC.

发明人： Anthony K. Stamper ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli

IPC分类号： H01L21/764 ,  H01L29/06 ,  H01L23/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762

摘要： The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

公开(公告)号：US10580689B2

公开(公告)日：2020-03-03

申请号：US15856525

申请日：2017-12-28

申请人： GLOBALFOUNDRIES INC.

发明人： James W. Adkisson ,  Anthony K. Stamper

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L27/06 ,  H01L23/485 ,  H01L21/768 ,  H01L21/8249 ,  H01L21/02

摘要： An advanced contact module for optimizing emitter and contact resistance and methods of manufacture are disclosed. The method includes forming a first contact via to a first portion of a first device. The method further includes filling the first contact via with metal material to form a first metal contact to the first portion of the first device. The method further includes forming additional contact vias to other portions of the first device and contacts of a second device. The method further includes cleaning the additional contact vias while protecting the first metal contact of the first portion of the first device. The method further includes filling the additional contact vias with metal material to form additional metal contacts to the other portions of the first device and the second device.

公开(公告)号：US10446643B2

公开(公告)日：2019-10-15

申请号：US15876727

申请日：2018-01-22

申请人： GLOBALFOUNDRIES INC.

发明人： Siva P. Adusumilli ,  Anthony K. Stamper ,  Laura J. Schutz ,  Cameron E. Luce

IPC分类号： H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762

摘要： The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.

公开(公告)号：US20190172846A1

公开(公告)日：2019-06-06

申请号：US16258714

申请日：2019-01-28

申请人： GLOBALFOUNDRIES INC.

发明人： Anthony K. Stamper ,  Steven M. Shank ,  Siva P. Adusumilli

IPC分类号： H01L27/12 ,  H01L49/02 ,  H01L21/762 ,  H01L29/06 ,  H01L27/06 ,  H01L29/45 ,  H01L29/08 ,  H01L21/265 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/02

摘要： Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions. Also disclosed is an IC structure formed using the method.

公开(公告)号：US10109599B2

公开(公告)日：2018-10-23

申请号：US15387120

申请日：2016-12-21

申请人： GLOBALFOUNDRIES Inc.

发明人： Cathryn J. Christiansen ,  Anthony K. Stamper ,  Tom C. Lee ,  Ian Mccallum-Cook

IPC分类号： H01L29/45 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

摘要： An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.

公开(公告)号：US10062748B1

公开(公告)日：2018-08-28

申请号：US15443276

申请日：2017-02-27

申请人： GLOBALFOUNDRIES INC.

发明人： Anthony K. Stamper ,  Vincent J. McGahay ,  Zhong-Xiang He

IPC分类号： H01L23/48 ,  H01L29/06 ,  H01L23/31 ,  H01L23/528

摘要： The present disclosure relates to semiconductor structures and, more particularly, to segmented guard-ring and chip edge seals and methods of manufacture. The structure includes: a guard ring structure formed in a low-k dielectric material; and an edge seal structure formed through the low-k dielectric material to at least a substrate underneath the low-k dielectric material.

公开(公告)号：US20180174982A1

公开(公告)日：2018-06-21

申请号：US15387120

申请日：2016-12-21

申请人： GLOBALFOUNDRIES Inc.

发明人： Cathryn J. Christiansen ,  Anthony K. Stamper ,  Tom C. Lee ,  Ian Mccallum-Cook

IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L29/45

CPC分类号： H01L23/562 ,  H01L23/5226 ,  H01L23/53257 ,  H01L29/45

摘要： An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.

公开(公告)号：US09922973B1

公开(公告)日：2018-03-20

申请号：US15611184

申请日：2017-06-01

申请人： GLOBALFOUNDRIES INC.

发明人： Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Thai Doan

IPC分类号： H01L21/76 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L27/02 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/761 ,  H01L21/764 ,  H01L21/02 ,  H01L21/763

CPC分类号： H01L27/088 ,  H01L21/761 ,  H01L21/763 ,  H01L21/764 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0603 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/1095

摘要： The present disclosure relates to semiconductor structures and, more particularly, to switches with deep trench depletion and isolation structures and methods of manufacture. The structure includes a bulk substrate with a fully depleted region below source and drain regions of at least one gate stack and confined by deep trench isolation structures lined with doped material.