公开(公告)号：US10411832B2

公开(公告)日：2019-09-10

申请号：US15336974

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Yang ,  Yang Liu ,  Jilei Yin ,  Wei Jiang

IPC: H04L1/00

Abstract: Disclosed are Ethernet physical layer devices (e.g., a transceiver, a receiver and a transmitter) with integrated physical coding and forward error correction sub-layers. Each physical layer device includes a physical coding sub-layer (PCS), a forward error correction sub-layer (FEC) and integration block(s). Each integration block halts, for some number of clock cycles, a data stream in portions of a data path (e.g., portions of a transmitter (TX) data path or portions a receiver (RX) data path) within the PCS and the FEC in order to compensate for processing of that data stream by a data processor (e.g., a code word mark (CWM) inserter or a CWM remover) contained in the portion of the data path within the FEC. Use of such integration block(s) eliminates the need for redundant components in the PCS and FEC, thereby reducing latency, costs and chip area consumption. Also disclosed are associated methods.

公开(公告)号：US10784976B2

公开(公告)日：2020-09-22

申请号：US16196970

申请日：2018-11-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kai Yang ,  Adrian Butter ,  Bin Sun ,  Yijian Qi ,  Jilei Yin

IPC: H04J3/06

Abstract: A system and apparatus for obtaining clock synchronization of networked devices and related method are provided. Embodiments include a computer-implemented system, including a primary device having a first high accuracy timestamping assist (HATA) unit attached to a first physical layer; a first time stamping unit; a first clock control; a first medium access control layer connected to the first time stamping unit and the first physical layer via a medium independent interface. A secondary device includes a second HATA unit attached to a second physical layer; a second timestamping unit; a second clock control. The first and second HATA units are configured to detect a departure time, an arrival time, or a combination thereof of a first alignment marker over transmitter serializer and receiver deserializer interfaces of a data transmission between the primary device and the secondary device.

公开(公告)号：US20180123733A1

公开(公告)日：2018-05-03

申请号：US15336974

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Yang ,  Yang Liu ,  Jilei Yin ,  Wei Jiang

IPC: H04L1/00

CPC classification number: H04L1/0052 ,  H04L1/0043

Abstract: Disclosed are Ethernet physical layer devices (e.g., a transceiver, a receiver and a transmitter) with integrated physical coding and forward error correction sub-layers. Each physical layer device includes a physical coding sub-layer (PCS), a forward error correction sub-layer (FEC) and integration block(s). Each integration block halts, for some number of clock cycles, a data stream in portions of a data path (e.g., portions of a transmitter (TX) data path or portions a receiver (RX) data path) within the PCS and the FEC in order to compensate for processing of that data stream by a data processor (e.g., a code word mark (CWM) inserter or a CWM remover) contained in the portion of the data path within the FEC. Use of such integration block(s) eliminates the need for redundant components in the PCS and FEC, thereby reducing latency, costs and chip area consumption. Also disclosed are associated methods.