公开(公告)号：US20180323113A1

公开(公告)日：2018-11-08

申请号：US16038977

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar PATIL ,  Katsunori ONISHI ,  Pei LIU ,  Chih-Chiang CHANG

IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/092 ,  H01L21/28

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/4966

Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.