公开(公告)号：US09564375B2

公开(公告)日：2017-02-07

申请号：US14054040

申请日：2013-10-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy Mann ,  Sandeep Puri ,  Sonia Ghosh ,  Anuj Gupta ,  Xusheng Wu

IPC: G06F17/50 ,  H01L21/66

CPC classification number: H01L22/14 ,  G01B2210/56 ,  G06F17/5063 ,  G06F17/5068

Abstract: Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths.

Abstract translation: 公开了用于提取晶体管沟道宽度的方法和设计结构。 实施例可以包括根据晶体管的拉出沟道宽度确定多个集成电路的晶体管的有效沟道宽度，以及基于有效沟道宽度确定目标晶体管的目标沟道宽度。

公开(公告)号：US08751985B1

公开(公告)日：2014-06-10

申请号：US13795198

申请日：2013-03-12

Applicant: Globalfoundries Inc.

Inventor： Sandeep Puri ,  Bipul C. Paul ,  Werner Juengling ,  Anurag Mittal

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Hierarchical layout versus schematic comparison with extraneous device elimination is provided. This includes obtaining a hierarchical layout netlist for a circuit design, the hierarchical layout netlist grouping arrayed devices of the circuit design into blocks repeated at a top level of a hierarchy of the hierarchical layout netlist. A modified hierarchical layout netlist defining active devices and connections thereof to top level pads of the circuit design is generated, in which extraneous devices are selectively removed from the obtained hierarchical layout netlist. The modified hierarchical layout netlist is verified against an input schematic netlist defining active devices of the circuit design and connections thereof to pads of the circuit design.

Abstract translation: 提供了层次布局与与外部设备消除的原理图比较。 这包括获得用于电路设计的分层布局网表，分层布局网表将电路设计的阵列设备分组成在分级布局网表的层次结构的顶层重复的块。 产生了将有源器件及其连接定义为电路设计的顶级焊盘的修改的分层布局网表，其中从获得的分层布局网表中选择性地移除了外来设备。 修改的分层布局网表针对定义电路设计的有源器件的输入原理图网表及其与电路设计的焊盘的连接来验证。