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    TIMING DRIVEN CELL SWAPPING
    3.
    发明申请
    TIMING DRIVEN CELL SWAPPING 审中-公开

    公开(公告)号：US20190236239A1

    公开(公告)日：2019-08-01

    申请号：US16257822

    申请日：2019-01-25

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： YEN-HUNG LIN

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5077

    摘要： A method for cell swapping is provided. A location for swapping a first cell is determined. One or more legal positions for cell placement are determined at the location. A plurality of cells is determined for of the plurality of legal positions. A second cell from the plurality of cells is determined based on timing information associated with each of the plurality. The first cell is swapped with the second cell.

    Universal Circuit Design Systems and Methods
    4.
    发明申请
    Universal Circuit Design Systems and Methods 审中-公开

    公开(公告)号：US20190213299A1

    公开(公告)日：2019-07-11

    申请号：US15864334

    申请日：2018-01-08

    申请人： Oracle International Corporation

    发明人： Jerome Gentillet ,  Harshad Desai ,  David Scott Green

    IPC分类号： G06F17/50 ,  G06F17/30

    CPC分类号： G06F17/5081 ,  G06F16/2455 ,  G06F17/5072

    摘要： A universal circuit design environment that designs universal circuits that can be applied to a variety of applications is disclosed. The system cross-references attribute requirements of each contemplated application against components to select application set components that are used to populate the universal design circuit environment for use in a universal circuit design. The set components are capable of satisfying every resolvable attribute requirement of the variety of applications, and the universal circuit may be designed with specialized inputs to set some attributes of the universal circuit. Preferably, the footprint of each set component and universal circuit is preserved between versions to allow for optimized updating between component versions.

    SEMICONDUCTOR PROCESS AND PERFORMANCE SENSOR
    5.
    发明申请
    SEMICONDUCTOR PROCESS AND PERFORMANCE SENSOR 审中-公开

    公开(公告)号：US20190213292A1

    公开(公告)日：2019-07-11

    申请号：US16242405

    申请日：2019-01-08

    申请人： Atlazo, Inc.

    发明人： Shahin Solki

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/505 ,  G06F17/5081 ,  G06F2217/80 ,  G06F2217/84

    摘要： Disclosed are techniques that can be used in a semiconductor chip to determine performance such as timing performance. Among other features, supply voltages and clock rates may be adjusted to accommodate the operating temperature and to compensate for the processing variations that occurred when that chip was produced, or may occur as the chip is used. The techniques include determining a series of variables that affect performance, determining the sensitivity of timing paths in the circuit to each variable, duplicating the most sensitive paths. A novel sensor circuit is produced that includes the sensitive paths, which can be used to determine when the chip is performing as required and when it is not, and adjusting one or more supply voltages and/or clock rates in a static or real time manner when the circuit is not performing as required.

    PROCESS VARIATION-AWARE SIZING-INCLUSIVE ANALOG LAYOUT RETARGETING WITH OPTICAL PROXIMITY CORRECTION
    6.
    发明申请
    PROCESS VARIATION-AWARE SIZING-INCLUSIVE ANALOG LAYOUT RETARGETING WITH OPTICAL PROXIMITY CORRECTION 审中-公开

    公开(公告)号：US20190188356A1

    公开(公告)日：2019-06-20

    申请号：US15848736

    申请日：2017-12-20

    申请人： LIHONG ZHANG ,  XUAN DONG

    发明人： LIHONG ZHANG ,  XUAN DONG

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5036 ,  G06F17/5063

    摘要： The present disclosure provides a method to maximize the overall chip yield. This method combines a PV-aware deterministic circuit sizing process with a hybrid OPC operation, and integrates them into an analog layout migration platform, which attempts to efficiently compose a layout by inheriting knowledge from a legacy layout and imposing new specifications, circuit sizing and constraints. The present method provides a sizing process, which explores robust circuit sizes under different PV conditions, especially considering mismatch effects on sensitive analog devices. The analog layout migration is conducted along the sizing flow for efficient layout synthesis with a unique benefit to better evaluation of the PV-related post-layout effects. After finishing the sizing process, a hybrid OPC operation, which adopts global rule-based OPC and local model-based OPC along with the PV-band shifting, is performed as a post-processing step. Thereafter, a target mask layout is created with fast processing time, high wafer image fidelity, low mask complexity, and robust circuit performance under PV conditions. This present method provides an efficient solution to layout synthesis with respect to analog ICs by combining the deterministic sizing process with fast analog layout migration and hybrid OPC operations.