公开(公告)号：US09836570B1

公开(公告)日：2017-12-05

申请号：US15173756

申请日：2016-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Atsushi Azuma ,  Yuping Cui ,  James A. Culp ,  Marco Facchini ,  Shaoning Yao

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: Semiconductor layout generation includes: calculating, for a design rule constraint, a slack value for a subset of elements of a proposed semiconductor layout; generating a plurality of alternative layouts, where each of the alternative layouts includes a variation of interdependent characteristics of the subset of elements and a slack value for the subset of elements of each of the alternative layouts is less than the calculated slack value of subset of elements of the proposed layout; and calculating, by the layout design module for each of the alternative layouts, a risk value indicating the alternative layout's risk of fabrication failure.

公开(公告)号：US20170351799A1

公开(公告)日：2017-12-07

申请号：US15173756

申请日：2016-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Atsushi Azuma ,  Yuping Cui ,  James A. Culp ,  Marco Facchini ,  Shaoning Yao

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: Semiconductor layout generation includes: calculating, for a design rule constraint, a slack value for a subset of elements of a proposed semiconductor layout; generating a plurality of alternative layouts, where each of the alternative layouts includes a variation of interdependent characteristics of the subset of elements and a slack value for the subset of elements of each of the alternative layouts is less than the calculated slack value of subset of elements of the proposed layout; and calculating, by the layout design module for each of the alternative layouts, a risk value indicating the alternative layout's risk of fabrication failure.