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公开(公告)号：US20210320650A1
公开(公告)日：2021-10-14
申请号：US16847807
申请日：2020-04-14
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor： Uttam SAHA , Mahbub RASHED
Abstract: The present disclosure relates to integrated circuits, and more particularly, to a low clock load dynamic dual output latch circuit and methods of operation. The structure includes: a plurality of dynamic clocked stacks which are configured to receive input data and provide a true logical value and a complement logical value; and a plurality of holding stacks which are configured to provide a hold signal to the dynamic clocked stacks and output the true logical value and the complement logical value in response to the hold signal being activated.
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