公开(公告)号：US11380373B1

公开(公告)日：2022-07-05

申请号：US17317938

申请日：2021-05-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mohamed A. Nour ,  Peter C. Paliwoda ,  Byoung-Woon B Min ,  Toshiaki Kirihata

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C8/10 ,  G11C16/04 ,  G11C11/22

Abstract: Disclosed is a memory structure including an array of memory cells and a read circuit. The read circuit includes two registers configured to capture and store two different digital-to-analog converter (DAC) codes, which correspond to two different reference currents that approximate two different output currents generated on a bitline during consecutive single-ended current sensing processes directed to the same selected memory cell but using different input voltages. Optionally, the read circuit can also include a current-voltage (I-V) slope calculator, which uses the two different DAC codes to calculate an I-V slope characteristic of the selected memory cell, and a bit generator, which performs a comparison of the I-V slope characteristic and a reference I-V slope characteristic and based on results of the comparison, generates and outputs a bit with a logic value that represents the data storage state of the selected memory cell. Also disclosed is an associated method.