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公开(公告)号：US20200275040A1
公开(公告)日：2020-08-27
申请号：US16859308
申请日：2020-04-27
Applicant: Google LLC
Inventor： Neeti Desai , Albert Meixner , Qiuling Zhu , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein
Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
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公开(公告)号：US20200186667A1
公开(公告)日：2020-06-11
申请号：US16786359
申请日：2020-02-10
Applicant: Google LLC
Inventor： Albert Meixner , Jason Rupert Redgrave , Ofer Shacham , Qiuling Zhu , Daniel Frederic Finchelstein
Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.
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公开(公告)号：US20190378239A1
公开(公告)日：2019-12-12
申请号：US16547801
申请日：2019-08-22
Applicant: Google LLC
Inventor： Qiuling Zhu , Ofer Shacham , Albert Meixner , Jason Rupert Redgrave , Daniel Frederic Finchelstein , David Patterson , Neeti Desai , Donald Stark , Edward Chang , William R. Mark
Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
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公开(公告)号：US10321077B2
公开(公告)日：2019-06-11
申请号：US15598027
申请日：2017-05-17
Applicant: Google LLC
Inventor： Neeti Desai , Albert Meixner , Qiuling Zhu , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein
Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
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公开(公告)号：US10291813B2
公开(公告)日：2019-05-14
申请号：US14694806
申请日：2015-04-23
Applicant: Google LLC
Inventor： Albert Meixner , Jason Rupert Redgrave , Ofer Shacham , Qiuling Zhu , Daniel Frederic Finchelstein
Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.
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Patent Agency Ranking
公开(公告)号：US10275253B2
公开(公告)日：2019-04-30
申请号：US15595632
申请日：2017-05-15
Applicant: Google LLC
Inventor： Albert Meixner , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein , Qiuling Zhu
Abstract: An apparatus that includes a program controller to fetch and issue instructions. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
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公开(公告)号：US09965824B2
公开(公告)日：2018-05-08
申请号：US14694828
申请日：2015-04-23
Applicant: Google LLC
Inventor： Qiuling Zhu , Ofer Shacham , Albert Meixner , Jason Rupert Redgrave , Daniel Frederic Finchelstein , David Patterson , Neeti Desai , Donald Stark , Edward T. Chang , William R. Mark
Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
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公开(公告)号：US12020027B2
公开(公告)日：2024-06-25
申请号：US17028097
申请日：2020-09-22
Applicant: Google LLC
Inventor： Ofer Shacham , David Patterson , William R. Mark , Albert Meixner , Daniel Frederic Finchelstein , Jason Rupert Redgrave
CPC classification number: G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/3885 , G06F9/3887 , G06N3/045 , G06N3/063 , G06T1/60 , G06T5/20 , G06T2200/28 , G06T2207/20084
Abstract: A method is described that includes executing a convolutional neural network layer on an image processor having an array of execution lanes and a two-dimensional shift register. The two-dimensional shift register provides local respective register space for the execution lanes. The executing of the convolutional neural network includes loading a plane of image data of a three-dimensional block of image data into the two-dimensional shift register. The executing of the convolutional neural network also includes performing a two-dimensional convolution of the plane of image data with an array of coefficient values by sequentially: concurrently multiplying within the execution lanes respective pixel and coefficient values to produce an array of partial products; concurrently summing within the execution lanes the partial products with respective accumulations of partial products being kept within the two dimensional register for different stencils within the image data; and, effecting alignment of values for the two-dimensional convolution within the execution lanes by shifting content within the two-dimensional shift register array.
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公开(公告)号：US10915773B2
公开(公告)日：2021-02-09
申请号：US15596286
申请日：2017-05-16
Applicant: Google LLC
Inventor： Edward Chang , Daniel Frederic Finchelstein , Szepo Robert Hung , Albert Meixner , Ofer Shacham
Abstract: A method is described that includes loading an array of content into a two-dimensional shift register. The two-dimensional shift register is coupled to an execution lane array. The method includes repeatedly performing a first sequence including: shifting with the shift register first content residing along a particular row or column into another parallel row or column where second content resides and performing operations with a particular corresponding row or column of the execution lane array on the first and second content. The method also includes repeatedly performing a second sequence including: shifting with the shift register content from a set of first locations along a resultant row or column that is parallel with the rows or columns of the first sequence into a corresponding set of second locations along the resultant row or column. The resultant row or column has values determined from the operations of the first sequence.
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公开(公告)号：US20210004232A1
公开(公告)日：2021-01-07
申请号：US17001097
申请日：2020-08-24
Applicant: Google LLC
Inventor： Albert Meixner , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein , Qiuling Zhu
Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
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