公开(公告)号：US10789202B2

公开(公告)日：2020-09-29

申请号：US15594502

申请日：2017-05-12

申请人： Google LLC

发明人： Jason Redgrave ,  Albert Meixner ,  Ji Kim ,  Ofer Shacham

IPC分类号： G06F15/80 ,  G06T1/20 ,  G06F15/173 ,  G06F1/3234

摘要： A method is described. The method includes configuring a first instance of object code to execute on a processor. The processor has multiple cores and an internal network. The internal network is configured in a first configuration that enables a first number of the cores to be communicatively coupled. The method also includes configuring a second instance of the object code to execute on a second instance of the processor. A respective internal network of the second instance of the processor is configured in a second configuration that enables a different number of cores to be communicatively coupled, wherein, same positioned cores on the processor and the second instance of the processor have same network addresses for the first and second configurations. A processor is also described having an internal network designed to enable the above method.

公开(公告)号：US20200275040A1

公开(公告)日：2020-08-27

申请号：US16859308

申请日：2020-04-27

申请人： Google LLC

发明人： Neeti Desai ,  Albert Meixner ,  Qiuling Zhu ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Daniel Frederic Finchelstein

IPC分类号： H04N5/369 ,  G06T1/60 ,  H04N5/91

摘要： An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.

公开(公告)号：US20200257639A1

公开(公告)日：2020-08-13

申请号：US16518503

申请日：2019-07-22

申请人： Google LLC

发明人： Vinod Chamarty ,  Xiaoyu Ma ,  Hongil Yoon ,  Keith Robert Pflederer ,  Weiping Liao ,  Benjamin Dodge ,  Albert Meixner ,  Allan Douglas Knies ,  Manu Gulati ,  Rahul Jagdish Thakur ,  Jason Rupert Redgrave

IPC分类号： G06F13/16 ,  G06F12/0815 ,  G06F12/0877 ,  G06F12/0811

摘要： Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.

公开(公告)号：US10719295B2

公开(公告)日：2020-07-21

申请号：US16687488

申请日：2019-11-18

申请人： Google LLC

发明人： Artem Vasilyev ,  Albert Meixner ,  Jason Rupert Redgrave

IPC分类号： G06F7/50 ,  G06T1/20 ,  G11C19/38 ,  G06F9/30 ,  G06F9/38

摘要： An execution unit is described. The execution unit includes an arithmetic logic unit (ALU) circuit having a first input to receive a first value and a second input to receive a second value. The ALU circuit includes circuitry to determine an absolute value of the first value and to add the absolute value to the second value. The first input is coupled to a first data path having register space and an output of another ALU of the execution unit circuit as alternative sources of the first value. The second input is coupled to a second data path having the register space as a source for the second value.

公开(公告)号：US20200186667A1

公开(公告)日：2020-06-11

申请号：US16786359

申请日：2020-02-10

申请人： Google LLC

发明人： Albert Meixner ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Qiuling Zhu ,  Daniel Frederic Finchelstein

IPC分类号： H04N1/32 ,  B41F15/08 ,  G06T1/60

摘要： A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.

公开(公告)号：US20200098083A1

公开(公告)日：2020-03-26

申请号：US16585834

申请日：2019-09-27

申请人： Google LLC

发明人： Hyunchul Park ,  Albert Meixner ,  Qiuling Zhu ,  William Mark

IPC分类号： G06T1/60 ,  G06F9/50 ,  G06F17/50 ,  G06T1/20 ,  G06F3/06 ,  G09G5/36

摘要： A method is described. The method includes simulating execution of an image processing application software program. The simulating includes intercepting kernel-to-kernel communications with simulated line buffer memories that store and forward lines of image data communicated from models of producing kernels to models of consuming kernels. The simulating further includes tracking respective amounts of image data stored in the respective line buffer memories over a simulation runtime. The method also includes determining respective hardware memory allocations for corresponding hardware line buffer memories from the tracked respective amounts of image data. The method also includes generating configuration information for an image processor to execute the image processing application software program. The configuration information describes the hardware memory allocations for the hardware line buffer memories of the image processor.

公开(公告)号：US10599407B2

公开(公告)日：2020-03-24

申请号：US16122801

申请日：2018-09-05

申请人： Google LLC

发明人： Albert Meixner

IPC分类号： G06F8/41 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38

摘要： A method is described that includes translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that is able to shift data along two different axis. The translating includes replacing the higher level instructions having the instruction format with lower level shift instructions that shift data within the shift register array structure.

公开(公告)号：US20200050486A1

公开(公告)日：2020-02-13

申请号：US16657656

申请日：2019-10-18

申请人： Google LLC

发明人： Hyunchul Park ,  Albert Meixner

IPC分类号： G06F9/50 ,  G06T1/20

摘要： A method is described. The method includes calculating data transfer metrics for kernel-to-kernel connections of a program having a plurality of kernels that is to execute on an image processor. The image processor includes a plurality of processing cores and a network connecting the plurality of processing cores. Each of the kernel-to-kernel connections include a producing kernel that is to execute on one of the processing cores and a consuming kernel that is to execute on another one of the processing cores. The consuming kernel is to operate on data generated by the producing kernel. The method also includes assigning kernels of the plurality of kernels to respective ones of the processing cores based on the calculated data transfer metrics.

公开(公告)号：US20190378239A1

公开(公告)日：2019-12-12

申请号：US16547801

申请日：2019-08-22

申请人： Google LLC

发明人： Qiuling Zhu ,  Ofer Shacham ,  Albert Meixner ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  David Patterson ,  Neeti Desai ,  Donald Stark ,  Edward Chang ,  William R. Mark

IPC分类号： G06T1/20 ,  G06T1/60 ,  H04N5/378 ,  H04N5/91

摘要： An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.

公开(公告)号：US10321077B2

公开(公告)日：2019-06-11

申请号：US15598027

申请日：2017-05-17

申请人： Google LLC

发明人： Neeti Desai ,  Albert Meixner ,  Qiuling Zhu ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Daniel Frederic Finchelstein

IPC分类号： H04N5/369 ,  G06T1/60 ,  H04N5/91

摘要： An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.