公开(公告)号：US06885591B2

公开(公告)日：2005-04-26

申请号：US10627843

申请日：2003-07-25

Applicant: Ge Nong

Inventor： Ge Nong

IPC: G11C11/406 ,  G11C11/4076 ,  G11C16/04

CPC classification number: G11C11/406 ,  G11C11/4076 ,  G11C2207/2245

Abstract: A method and circuit buffer for temporarily holding packets of information. The buffer may include a first memory and a second memory for holding the packets of information. The first memory may be a read-once memory in which data stored in the first memory is destroyed upon being read therefrom the first time. The second memory may be a memory in which stored data therein is not destroyed following the data being read from the second memory the first time. The buffer includes at least one queue. The head-of-line packet of the at least one queue is stored in the second memory. Incoming fanout splitting packets are stored in the second memory and other incoming packets are initially stored in the first memory.

Abstract translation: 一种用于临时保存信息包的方法和电路缓冲器。 缓冲器可以包括用于保持信息分组的第一存储器和第二存储器。 第一存储器可以是一读存储器，其中存储在第一存储器中的数据在第一次从其读取时被破坏。 第二存储器可以是其中存储的数据在第一次从第二存储器读取数据之后不被破坏的存储器。 缓冲区至少包括一个队列。 该至少一个队列的行头包被存储在第二存储器中。 传入的扇出分组包存储在第二存储器中，并且其他传入分组最初存储在第一存储器中。

公开(公告)号：US07154885B2

公开(公告)日：2006-12-26

申请号：US10036807

申请日：2001-12-31

Applicant: Ge Nong

Inventor： Ge Nong

IPC: H04L12/56

CPC classification number: H04L12/5601 ,  H04L49/106 ,  H04L2012/5679 ,  H04L2012/5681 ,  H04L2012/5683

Abstract: A packet switch for switching cells comprising fixed-size data packets. The packet switch comprises: 1) N input ports for receiving and storing cells in input queues; 2) N output ports for receiving and storing cells from the N input ports in output queues; 3) a switch fabric for transferring the cells from the N input ports to the N output ports, the switch fabric comprising an internally buffered crossbar having N×N internal buffers, wherein each internal buffer is associated with a crosspoint of one of the N input ports and one of the N output ports; and 4) a scheduling controller for selecting a first one of a plurality of queued head-of-line (HOL) cells from the input queues to be transmitted to a first one of the N×N internal buffers according to a fair queuing algorithm in which each of the queued HOL cells is allocated a weight of Rij and wherein the scheduling controller selects a first one of a plurality of HOL cells buffered in a second one of the N×N internal buffers to be transmitted to a first one of the output queues according to a fair queuing algorithm in which each of the internally buffered HOL cells is allocated a weight of Rij.

Abstract translation: 用于切换小区的分组交换机，包括固定大小的数据分组。 分组交换机包括：1）用于在输入队列中接收和存储小区的N个输入端口; 2）N个输出端口，用于从输出队列中的N个输入端口接收和存储单元; 3）用于将单元从N个输入端口传送到N个输出端口的交换结构，交换结构包括具有N×N内部缓冲器的内部缓冲交叉开关，其中每个内部缓冲器与N个输入端口之一的交叉点相关联， N个输出端口之一; 以及4）调度控制器，用于根据公平排队算法从输入队列中选择要发送到N×N内部缓冲器中的第一个的输入队列中的第一个排队的行头（HOL）单元， 分配排队的HOL小区的权重为R ij ij，并且其中调度控制器选择在N×N个内部缓冲器中的第二个缓冲器中缓冲的多个HOL单元中的第一个被发送到第一个 根据公平排队算法的输出队列之一，其中每个内部缓冲的HOL单元被分配为R ij ij的权重。

公开(公告)号：US20050018492A1

公开(公告)日：2005-01-27

申请号：US10627843

申请日：2003-07-25

Applicant: Ge Nong

Inventor： Ge Nong

IPC: G11C11/406 ,  G11C11/4076 ,  G11C16/04

CPC classification number: G11C11/406 ,  G11C11/4076 ,  G11C2207/2245

Abstract: A method and circuit are disclosed for a buffer for temporarily holding packets of information. The buffer may include a first memory and a second memory for holding the packets of information. The first memory may be a read-once memory in which data stored in the first memory is destroyed upon being read therefrom the first time. The second memory may be a memory in which stored data therein is not destroyed following the data being read from the second memory the first time. The buffer includes at least one queue. The head-of-line packet of the at least one queue is stored in the second memory. Incoming fanout splitting packets are stored in the second memory and other incoming packets are initially stored in the first memory.

Abstract translation: 公开了用于暂时保存信息包的缓冲器的方法和电路。 缓冲器可以包括用于保持信息分组的第一存储器和第二存储器。 第一存储器可以是一读存储器，其中存储在第一存储器中的数据在第一次从其读取时被破坏。 第二存储器可以是其中存储的数据在第一次从第二存储器读取数据之后不被破坏的存储器。 缓冲区至少包括一个队列。 该至少一个队列的行头包被存储在第二存储器中。 传入的扇出分组包存储在第二存储器中，并且其他传入分组最初存储在第一存储器中。

公开(公告)号：US08432927B2

公开(公告)日：2013-04-30

申请号：US10036809

申请日：2001-12-31

Applicant: Ge Nong

Inventor： Ge Nong

IPC: H04L12/56

CPC classification number: H04L49/1576 ,  H04L12/5601 ,  H04L2012/5679

Abstract: A fixed-size data packet switch comprising: 1) N input ports for receiving incoming fixed-size data packets at a first data rate and outputting the fixed-size data packets at the first data rate; 2) N output ports for receiving fixed-size data packets at the first data rate and outputting the fixed-size data packets at the first data rate; and 3) a switch fabric interconnecting the N input ports and the N output ports. The switch fabric comprises: a) N input buffers for receiving incoming fixed-size data packets at the first data rate and outputting the fixed-size data packets at a second data rate equal to at least twice the first data rate; b) N output buffers for receiving fixed-size data packets at the second data rate and outputting the fixed-size data packets at the first data rate; and c) a bufferless, non-blocking interconnecting network for receiving from the N input buffers the fixed-size data packets at the second data rate and transferring the fixed-size data packets to the N output buffers at the second data rate.

公开(公告)号：US07206325B2

公开(公告)日：2007-04-17

申请号：US10141560

申请日：2002-05-08

Applicant: Ge Nong

Inventor： Ge Nong

IPC: H04J3/16

CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L49/3081 ,  H04L2012/5652 ,  H04L2012/5681

Abstract: A packet switch capable of receiving fixed size data cells from N input ports and transmitting the fixed size data cells to N output ports. The packet switch comprises: 1) a frame deserializer for receiving the data cells as serial bits from the N input ports and transmitting the data cells as parallel bits in data frames containing a plurality of data cells, wherein each of the plurality of data cells in each data frame are destined for a common output port; 2) a frame serializer for receiving the data frames and transmitting the plurality of data cells in the data frames as serial bits to the N output ports; and 3) a shared buffer coupling the frame deserializer and the frame serializer for receiving and buffering the data frames from the frame deserializer and transmitting the buffered data frames to the frame serializer.

Abstract translation: 一种分组交换机，能够从N个输入端口接收固定大小的数据信元，并将固定大小的数据信元发送到N个输出端口。 分组交换机包括：1）帧解串器，用于从N个输入端口接收作为串行比特的数据单元，并将数据单元作为包含多个数据单元的数据帧中的并行比特发送，其中多个数据单元中的每一个在 每个数据帧都注定为公共输出端口; 2）一种帧序列化器，用于接收数据帧并将数据帧中的多个数据信元作为串行位发送到N个输出端口; 以及3）耦合帧解串器和帧串行器的共享缓冲器，用于从帧解串器接收和缓冲数据帧，并将缓冲的数据帧发送到帧序列化器。