公开(公告)号：US11824683B2

公开(公告)日：2023-11-21

申请号：US17657081

申请日：2022-03-29

Applicant: Microsoft Technology Licensing, LLC

Inventor： Pradeep Sindhu ,  Jean-Marc Frailong ,  Bertrand Serlet ,  Wael Noureddine ,  Felix A. Marti ,  Deepak Goel ,  Rajan Goyal

IPC: G06F13/12 ,  H04L12/46 ,  G06F13/16 ,  G06F13/42 ,  G06F12/0817 ,  H04L49/253 ,  H04L49/10 ,  G06F9/54 ,  H04L12/54 ,  H04L45/02 ,  G06F12/0811 ,  H04L12/70

CPC classification number: H04L12/4633 ,  G06F9/546 ,  G06F12/0817 ,  G06F13/1668 ,  G06F13/4282 ,  H04L12/56 ,  H04L45/02 ,  H04L49/10 ,  H04L49/253 ,  G06F12/0811 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2213/0026 ,  H04L2012/5619 ,  H04L2012/5681

Abstract: A new processing architecture is described in which a data processing unit (DPU) is utilized within a device. Unlike conventional compute models that are centered around a central processing unit (CPU), example implementations described herein leverage a DPU that is specially designed and optimized for a data-centric computing model in which the data processing tasks are centered around, and the primary responsibility of, the DPU. For example, various data processing tasks, such as networking, security, and storage, as well as related work acceleration, distribution and scheduling, and other such tasks are the domain of the DPU. The DPU may be viewed as a highly programmable, high-performance input/output (I/O) and data-processing hub designed to aggregate and process network and storage I/O to and from multiple other components and/or devices. This frees resources of the CPU, if present, for computing-intensive tasks.

公开(公告)号：US11799689B2

公开(公告)日：2023-10-24

申请号：US17353233

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： George Milescu ,  Silviu Petria ,  Andra Paraschiv

IPC: H04L12/54 ,  H04L12/707 ,  H04L45/24 ,  H04L47/283 ,  H04L47/20 ,  H04L45/12 ,  H04L45/00 ,  H04L12/70

CPC classification number: H04L12/5601 ,  H04L45/12 ,  H04L45/24 ,  H04L45/38 ,  H04L47/20 ,  H04L47/283 ,  H04L2012/568 ,  H04L2012/5627 ,  H04L2012/5681 ,  H04L2012/5684

Abstract: One embodiment provides an apparatus. The apparatus includes client traffic management (CTM) logic. The CTM logic is to trigger implementation of a selected network traffic flow related to the client device, the triggering based, at least in part, on a network traffic flow related to the client device. The network traffic flow is associated with a connection and includes at least one subflow. Each subflow is carried by a respective path associated with the connection. The triggering includes at least one of constraining and/or adjusting an allowable throughput at a service provider for one or more of the at least one subflow. The selected traffic policy is to be implemented in a transport layer.

公开(公告)号：US11683251B2

公开(公告)日：2023-06-20

申请号：US17699963

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Eugene Yasman ,  Nir Gerber ,  Sumit Mohan ,  Jean-Pierre Giacalone

IPC: H04L43/087 ,  H04L49/9005 ,  H04L49/90 ,  H04L49/9047 ,  H04L43/16 ,  H04L12/70

CPC classification number: H04L43/087 ,  H04L43/16 ,  H04L49/9005 ,  H04L49/9021 ,  H04L49/9052 ,  H04L49/9078 ,  H04L2012/5681

Abstract: Technologies for low-latency data streaming include a computing device having a processor that includes a producer and a consumer. The producer generates a data item, and in a local buffer producer mode adds the data item to a local buffer, and in a remote buffer producer mode adds the data item to a remote buffer. When the local buffer is full, the producer switches to the remote buffer producer mode, and when the remote buffer is below a predetermined low threshold, the producer switches to the local buffer producer mode. The consumer reads the data item from the local buffer while operating in a local buffer consumer mode and reads the data item from the remote buffer while operating in a remote buffer consumer mode. When the local buffer is above a predetermined high threshold, the consumer may switch to a catch-up operating mode. Other embodiments are described and claimed.

公开(公告)号：US20180248714A1

公开(公告)日：2018-08-30

申请号：US15756924

申请日：2015-09-28

Applicant: INTEL CORPORATION

Inventor： GEORGE MILESCU ,  SILVIU PETRIA ,  ANDRA PARASCHIV

IPC: H04L12/54 ,  H04L12/707 ,  H04L12/841 ,  H04L12/813

CPC classification number: H04L12/5601 ,  H04L45/12 ,  H04L45/24 ,  H04L45/38 ,  H04L47/20 ,  H04L47/283 ,  H04L2012/5627 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5684

Abstract: One embodiment provides an apparatus. The apparatus includes client traffic management (CTM) logic. The CTM logic is to trigger implementation of a selected network traffic flow related to the client device, the triggering based, at least in part, on a network traffic flow related to the client device. The network traffic flow is associated with a connection and includes at least one subflow. Each subflow is carried by a respective path associated with the connection. The triggering includes at least one of constraining and/or adjusting an allowable throughput at a service provider for one or more of the at least one subflow. The selected traffic policy is to be implemented in a transport layer.

公开(公告)号：US09602568B2

公开(公告)日：2017-03-21

申请号：US14822816

申请日：2015-08-10

Applicant: BROADCOM CORPORATION

Inventor： Rajesh Shankarrao Mamidwar ,  Sanjeev Sood ,  Anand Tongle ,  David Wu ,  Prashant Katre

IPC: G06F15/16 ,  H04L29/06 ,  H04L29/08 ,  H04L12/931 ,  H04L12/70 ,  H04L12/933 ,  H04L12/861 ,  H04L1/18 ,  H04L12/883 ,  H04L12/64 ,  H04L12/879

CPC classification number: H04L65/604 ,  H04L1/1874 ,  H04L49/103 ,  H04L49/206 ,  H04L49/35 ,  H04L49/9021 ,  H04L49/9026 ,  H04L49/9036 ,  H04L49/9047 ,  H04L65/607 ,  H04L67/32 ,  H04L2012/5678 ,  H04L2012/5681 ,  H04L2012/6489

Abstract: A system for adaptive audio video (AV) stream processing may include at least one processor and a switch device. The switch device may be configured to route AV traffic to the processor, and to receive AV traffic from the processor and provide the AV traffic to a client device via one or more channels. The processor may monitor a transcoder buffer depth and depths of buffers associated with channels over which the AV traffic is being transmitted. The processor may adaptively modify one or more attributes associated with the AV traffic based at least on the monitored buffer depths. For example, the processor may adaptively adjust a bit rate associated with transcoding the AV traffic based at least on the transcoder buffer depth. The processor may utilize the depths of the buffers associated with the channels to adaptively adjust the amount of AV traffic provided for transmission over the channels.

公开(公告)号：US09337952B2

公开(公告)日：2016-05-10

申请号：US13867968

申请日：2013-04-22

Applicant: Somnath Paul ,  Sriram R. Vangal

Inventor： Somnath Paul ,  Sriram R. Vangal

IPC: H04L1/00 ,  H03K19/00 ,  G06F11/26 ,  G11C29/00 ,  G11C29/02 ,  G06F13/16 ,  H04L12/70

CPC classification number: G06F11/0787 ,  G06F5/065 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/1407 ,  G06F11/1645 ,  G06F11/26 ,  G06F13/1673 ,  G06F13/1689 ,  G06F2205/067 ,  G11C29/003 ,  G11C29/023 ,  G11C29/028 ,  H03K19/00 ,  H04L1/00 ,  H04L2012/5681 ,  Y02D10/14

Abstract: Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.

Abstract translation: 描述了一种装置，包括：第一顺序单元; 与第一顺序单元并联耦合的第一队列，使得第一队列和第一顺序单元接收第一输入，用于对第一输入进行双倍采样的第一序列; 比较单元，用于接收来自第一顺序单元的输出; 以及由前一周期的写指针控制的第一选择单元，所述第一选择单元接收所述第一队列的每个存储单元的输出，其中所述第一选择单元生成用于由所述第一比较单元进行比较的输出。

公开(公告)号：US20150350285A1

公开(公告)日：2015-12-03

申请号：US14822816

申请日：2015-08-10

Applicant: BROADCOM CORPORATION

Inventor： Rajesh Shankarrao MAMIDWAR ,  Sanjeev SOOD ,  Anand TONGLE ,  David WU ,  Prashant KATRE

IPC: H04L29/06 ,  H04L29/08

CPC classification number: H04L65/604 ,  H04L1/1874 ,  H04L49/103 ,  H04L49/206 ,  H04L49/35 ,  H04L49/9021 ,  H04L49/9026 ,  H04L49/9036 ,  H04L49/9047 ,  H04L65/607 ,  H04L67/32 ,  H04L2012/5678 ,  H04L2012/5681 ,  H04L2012/6489

Abstract: A system for adaptive audio video (AV) stream processing may include at least one processor and a switch device. The switch device may be configured to route AV traffic to the processor, and to receive AV traffic from the processor and provide the AV traffic to a client device via one or more channels. The processor may monitor a transcoder buffer depth and depths of buffers associated with channels over which the AV traffic is being transmitted. The processor may adaptively modify one or more attributes associated with the AV traffic based at least on the monitored buffer depths. For example, the processor may adaptively adjust a bit rate associated with transcoding the AV traffic based at least on the transcoder buffer depth. The processor may utilize the depths of the buffers associated with the channels to adaptively adjust the amount of AV traffic provided for transmission over the channels.

公开(公告)号：US20150106498A1

公开(公告)日：2015-04-16

申请号：US14577132

申请日：2014-12-19

Applicant: The MathWorks, Inc.

Inventor： Edward W. GULLEY ,  Joseph F. HICKLIN ,  James N. GONTHIER ,  John R. LANGLEY ,  Joseph P. CONTI

IPC: H04L29/08

CPC classification number: H04L67/32 ,  G06F9/5027 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5055 ,  G06F2209/5011 ,  G06F2209/5013 ,  G06F2209/5015 ,  H04L49/9005 ,  H04L49/9047 ,  H04L67/10 ,  H04L2012/5678 ,  H04L2012/5681 ,  H04L2012/6489

Abstract: Exemplary embodiments may employ techniques for dynamically dispatching requests to resources operating in a distributed computing environment, such as a computing cloud, according to one or more policies. Embodiments may further dynamically adjust resources in the computing environment using predictive models that use current loads as an input. Embodiments may still further maintain a state for a processing environment independent of the type or configuration of a device used to access the environment on behalf of a user.

Abstract translation: 示例性实施例可以采用用于根据一个或多个策略来动态地分派对在分布式计算环境（例如计算云）中操作的资源的请求的技术。 实施例可以使用使用当前负载作为输入的预测模型来进一步动态地调整计算环境中的资源。 实施例还可以进一步保持与用于代表用户访问环境的设备的类型或配置无关的处理环境的状态。

公开(公告)号：US08918511B2

公开(公告)日：2014-12-23

申请号：US13485836

申请日：2012-05-31

Applicant: Edward Whittington Gulley ,  Joseph F. Hicklin ,  James N. Gonthier ,  John Richard Langley ,  Joseph Conti

Inventor： Edward Whittington Gulley ,  Joseph F. Hicklin ,  James N. Gonthier ,  John Richard Langley ,  Joseph Conti

IPC: G06F15/173 ,  G06F9/50 ,  H04L12/70 ,  H04L12/861 ,  H04L12/64

CPC classification number: H04L67/32 ,  G06F9/5027 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5055 ,  G06F2209/5011 ,  G06F2209/5013 ,  G06F2209/5015 ,  H04L49/9005 ,  H04L49/9047 ,  H04L67/10 ,  H04L2012/5678 ,  H04L2012/5681 ,  H04L2012/6489

Abstract: Exemplary embodiments may employ techniques for dynamically dispatching requests to resources operating in a distributed computing environment, such as a computing cloud, according to one or more policies. Embodiments may further dynamically adjust resources in the computing environment using predictive models that use current loads as an input. Embodiments may still further maintain a state for a processing environment independent of the type or configuration of a device used to access the environment on behalf of a user.

Abstract translation: 示例性实施例可以采用用于根据一个或多个策略来动态地分派对在分布式计算环境（例如计算云）中操作的资源的请求的技术。 实施例可以使用使用当前负载作为输入的预测模型来进一步动态地调整计算环境中的资源。 实施例还可以进一步保持与用于代表用户访问环境的设备的类型或配置无关的处理环境的状态。

公开(公告)号：US20140269298A1

公开(公告)日：2014-09-18

申请号：US13802838

申请日：2013-03-14

Applicant: RALINK TECHNOLOGY CORP.

Inventor： Kuo-Cheng Lu

IPC: H04L12/801

CPC classification number: H04L47/12 ,  H04L49/3027 ,  H04L49/505 ,  H04L49/90 ,  H04L2012/5681

Abstract: A network processor for processing packet switching in a network switching system is disclosed. The network processor includes a first memory for storing a first packet among a plurality of packets; a second memory for storing a second packet among the plurality of packets; and a memory selecting unit for selecting the first memory or the second memory for storing each of the plurality of packets according to whether a traffic of the network switching system is congested; wherein attributes of the first memory and the second memory are different.

Abstract translation: 公开了一种用于在网络交换系统中处理分组交换的网络处理器。 网络处理器包括用于存储多个分组中的第一分组的第一存储器; 用于在所述多个分组中存储第二分组的第二存储器; 以及存储选择单元，用于根据网络交换系统的业务是否拥塞来选择用于存储多个分组中的每一个的第一存储器或第二存储器; 其中第一存储器和第二存储器的属性不同。