Method and system for measuring critical dimension and monitoring fabrication uniformity
    1.
    发明授权
    Method and system for measuring critical dimension and monitoring fabrication uniformity 有权
    测量临界尺寸和监测制造均匀性的方法和系统

    公开(公告)号:US09100553B2

    公开(公告)日:2015-08-04

    申请号:US13785256

    申请日:2013-03-05

    Abstract: A method for measuring critical dimension (CD) includes steps of: scanning at least one area of interest of a die to obtain at least one scanned image; aligning the scanned image to at least one designed layout pattern to identify a plurality of borders within the scanned image; and averaging distances each measured from the border or the plurality of borders of a pattern associated with a specific type of CD corresponding to the designed layout pattern to obtain a value of CD of the die. The value of critical dimensions of dies can be obtained from the scanned image with lower resolution which is obtained by relatively higher scanning speed, so the above-mentioned method can obtain value of CD for every die within entire wafer to monitor the uniformity of the semiconductor manufacturing process within an acceptable inspection time.

    Abstract translation: 用于测量临界尺寸(CD)的方法包括以下步骤:扫描模具的至少一个感兴趣区域以获得至少一个扫描图像; 将扫描图像对准至少一个设计的布局图案,以识别扫描图像内的多个边界; 以及从与设计的布局图案对应的特定类型的CD相关联的图案的边界或多个边界测量的平均距离,以获得模具的CD的值。 可以通过相对较高的扫描速度获得的具有较低分辨率的扫描图像获得模具的临界尺寸的值,因此上述方法可以获得整个晶片内每个管芯的CD值,以监测半导体的均匀性 制造过程在可接受的检验时间内。

    Method and system for measuring critical dimension and monitoring fabrication uniformity

    公开(公告)号:US09041795B2

    公开(公告)日:2015-05-26

    申请号:US13785222

    申请日:2013-03-05

    Abstract: A method for measuring critical dimension (CD) includes steps of: scanning at least one area of interest of a die to obtain at least one scanned image; aligning the scanned image to at least one designed layout pattern to identify a plurality of borders within the scanned image; and averaging distances each measured from the border or the plurality of borders of a pattern associated with a specific type of CD corresponding to the designed layout pattern to obtain a value of CD of the die. The value of critical dimensions of dies can be obtained from the scanned image with lower resolution which is obtained by relatively higher scanning speed, so the above-mentioned method can obtain value of CD for every die within entire wafer to monitor the uniformity of the semiconductor manufacturing process within an acceptable inspection time.

    Method and system for measuring critical dimension and monitoring fabrication uniformity

    公开(公告)号:US09282293B2

    公开(公告)日:2016-03-08

    申请号:US13785240

    申请日:2013-03-05

    Abstract: A method for measuring critical dimension (CD) includes steps of: scanning at least one area of interest of a die to obtain at least one scanned image; aligning the scanned image to at least one designed layout pattern to identify a plurality of borders within the scanned image; and averaging distances each measured from the border or the plurality of borders of a pattern associated with a specific type of CD corresponding to the designed layout pattern to obtain a value of CD of the die. The value of critical dimensions of dies can be obtained from the scanned image with lower resolution which is obtained by relatively higher scanning speed, so the above-mentioned method can obtain value of CD for every die within entire wafer to monitor the uniformity of the semiconductor manufacturing process within an acceptable inspection time.

    Structure for inspecting defects in word line array fabricated by SADP process and method thereof
    4.
    发明授权
    Structure for inspecting defects in word line array fabricated by SADP process and method thereof 有权
    用于检查由SADP工艺制造的字线阵列中的缺陷的结构及其方法

    公开(公告)号:US08748814B1

    公开(公告)日:2014-06-10

    申请号:US13826015

    申请日:2013-03-14

    Inventor: Hong Xiao Jack Jau

    CPC classification number: H01J37/28 G01R31/024 H01J2237/24578 H01J2237/2817

    Abstract: This invention provides a test structure for inspecting word line array fabricated by SADP process, wherein the test structure comprises a contour circuit to cover one end of the WL array, and is alternatively float and ground to the word line array. The word line array then can be inspected by using E-beam inspection tool to identify open and short defects.

    Abstract translation: 本发明提供了一种用于检查由SADP工艺制造的字线阵列的测试结构,其中测试结构包括覆盖WL阵列的一端的轮廓线,并且交替地浮动并接地到字线阵列。 然后可以使用电子束检查工具来检查字线阵列,以识别开路和短路缺陷。

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