METHOD FOR DESIGNING TEST CIRCUIT AND ELECTRONIC DEVICE

    公开(公告)号:US20240249054A1

    公开(公告)日:2024-07-25

    申请号:US18426293

    申请日:2024-01-29

    CPC classification number: G06F30/333 G06F30/323

    Abstract: A method for designing a test circuit, includes determining a feature of a to-be-tested circuit based on data representing the to-be-tested circuit. The method further includes determining switch distribution for the to-be-tested circuit based on the feature of the to-be-tested circuit. The switch distribution represents distribution, in a two-dimensional switch matrix circuit, of a plurality of switches that are in a test circuit and that are coupled to a plurality of scan chains of the to-be-tested circuit. The switch matrix circuit includes a plurality of rows and a plurality of columns, any one of the plurality of rows has at least one of the plurality of switches, and any one of the plurality of columns has at least one of the plurality of switches.

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