公开(公告)号：US20240362393A1

公开(公告)日：2024-10-31

申请号：US18139659

申请日：2023-04-26

Applicant: Xilinx, Inc.

Inventor： Apurva Abhijit Mirashi ,  Veeresh Pratap Singh ,  Meghraj Kalase ,  Srinivasan Dasasathyan

IPC: G06F30/394 ,  G06F30/31 ,  G06F30/323 ,  G06F30/327 ,  G06F30/392

CPC classification number: G06F30/394 ,  G06F30/31 ,  G06F30/323 ,  G06F30/327 ,  G06F30/392

Abstract: A congestion prediction machine learning model is trained to generate, prior to placement, a prediction value indicative of a congestion level likely to result from placement and routing of a netlist based on features of the netlist. In response to the prediction value indicating the congestion level is greater than a threshold, a design tool determines an implementation-flow action and performs the implementation-flow action to generate implementation data that is suitable for making an integrated circuit.

公开(公告)号：US12039240B2

公开(公告)日：2024-07-16

申请号：US17517322

申请日：2021-11-02

Applicant: REALTEK SEMICONDUCTOR CORP.

Inventor： Hsing-Han Tseng ,  Yung-Jen Chen ,  Yu-Lan Lo

IPC: G06F30/3312 ,  G06F30/323 ,  G06F30/327 ,  G06F119/12

CPC classification number: G06F30/3312 ,  G06F30/323 ,  G06F30/327 ,  G06F2119/12

Abstract: An integrated circuit simulation method is performed by a processor and includes: obtaining a register transfer level (RTL) waveform set obtained by performing an RTL simulation based on a circuit, where the circuit is generated in an RTL design stage and includes a register having an internal net and a data output port, and the RTL waveform set includes a first waveform corresponding to the data output port of the register; obtaining a netlist and delay information obtained by performing a logic synthesis based on the circuit, where the netlist includes a first node and a second node, the first node corresponds to the internal net of the register, and the second node corresponds to the data output port of the register; applying the first waveform to the first node; and triggering the register according to the delay information to obtain a second waveform at the second node.

公开(公告)号：US11983474B1

公开(公告)日：2024-05-14

申请号：US17561371

申请日：2021-12-23

Applicant: Synopsys, Inc.

Inventor： Parijat Biswas ,  Badri Gopalan ,  Enzhi Ni ,  Danish Jawed ,  Ying Chen ,  Jiang Chen

IPC: G06F30/30 ,  G01R31/3183 ,  G06F30/323 ,  G06F30/3308

CPC classification number: G06F30/3308 ,  G01R31/31835 ,  G01R31/318357 ,  G06F30/323

Abstract: A method for verifying an integrated circuit (IC) design described in a hardware description or hardware verification language (HDHVL) is provided. The method includes identifying connections between random variables and coverage areas of the IC design, as described in HDHVL code, the connections being identified by determining which coverage areas of the IC design will be influenced during simulation by which random variables. The method can further include storing the identified connections in a database, and using, by a processor, connections retrieved from the database to simulate and verify the coverage areas of the IC design.

公开(公告)号：US20240061035A1

公开(公告)日：2024-02-22

申请号：US18071080

申请日：2022-11-29

Applicant: Synopsys, Inc.

Inventor： Mayukh BHATTACHARYA ,  Jonti TALUKDAR ,  Shan YUAN ,  Huiping HUANG

IPC: G01R31/28 ,  G06F30/323 ,  G06F30/3308

CPC classification number: G01R31/2848 ,  G06F30/323 ,  G06F30/3308

Abstract: A method of determining defect sensitization includes parsing a netlist of a circuit design to determine a plurality of potential defects and partitioning the circuit design into a plurality of blocks. The method also includes generating a graph representing the circuit design and determining a transitive closure of the graph. The method further includes grouping the plurality of potential defects to produce a plurality of groups of potential defects and selecting a potential defect from each group of the plurality of groups to form a simulation group of potential defects. The method also includes simulating the circuit design by injecting, into the circuit design, every potential defect of the simulation group to produce a set of outputs of the plurality of blocks and determining a defect sensitization for the simulation group of potential defects based on the set of outputs of the plurality of blocks.

公开(公告)号：US11853665B2

公开(公告)日：2023-12-26

申请号：US17490700

申请日：2021-09-30

Applicant: Synopsys, Inc.

Inventor： Parijat Biswas ,  Minakshi Chakravorty ,  Sitikant Sahu

IPC: G06F30/323

CPC classification number: G06F30/323

Abstract: Hardware description language (HDL) code for an integrated circuit (IC) design may be parsed to obtain an IC design parse tree. A transformation pattern may include a first pattern and a second pattern. The transformation pattern may be parsed to obtain a transformation pattern parse tree. The IC design parse tree and the transformation pattern parse tree may be used to identify a portion of the HDL code that matches the first pattern. The identified portion of the HDL code may be transformed based on the second pattern to obtain a transformed portion of the HDL code. The portion of the HDL code may be replaced by the transformed portion of the HDL code.

公开(公告)号：US11699010B2

公开(公告)日：2023-07-11

申请号：US17365468

申请日：2021-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

Inventor： Sandeep Kumar Goel ,  Ankita Patidar ,  Yun-Han Lee

IPC: G06F30/323 ,  G06F30/3323 ,  G06F30/392 ,  G06F30/394 ,  G03F1/70 ,  G06F119/12

CPC classification number: G06F30/323 ,  G03F1/70 ,  G06F30/3323 ,  G06F30/392 ,  G06F30/394 ,  G06F2119/12

Abstract: A method of manufacturing a semiconductor device includes reducing errors in a migration of a first netlist to a second netlist, the first netlist corresponding to a first semiconductor process technology (SPT), the second first netlist corresponding to a second SPT, the first and second netlists each representing a same circuit design, the reducing errors including: inspecting a timing constraint list corresponding to the second netlist for addition candidates; generating a first version of the second netlist having a first number of comparison points relative to a logic equivalence check (LEC) context, the first number of comparison points being based on the addition candidates; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

公开(公告)号：US20230177244A1

公开(公告)日：2023-06-08

申请号：US18076007

申请日：2022-12-06

Applicant: Synopsys, Inc.

Inventor： Prasun Das ,  Pratik Mahajan ,  Alfred Koelbl ,  Henna Arora

IPC: G06F30/3323 ,  G06F30/323

CPC classification number: G06F30/3323 ,  G06F30/323

Abstract: A method of verifying connectivity in a circuit design, includes, in part, receiving a netlist of the circuit design; designating a plurality of destination nodes associated with the netlist; for each of the plurality of destination nodes, identifying one or more source nodes that are traversed from the destination node; for each source node identified as traversed from the destination node: transforming the netlist by including a first multiplexer having a first input terminal receiving a first variable logic value and an output terminal coupled to the source node; and enabling the first multiplexer to pass the first variable value to the destination node from the source node in order to check for connectivity between the source node and the destination node.

公开(公告)号：US20240160818A1

公开(公告)日：2024-05-16

申请号：US17985735

申请日：2022-11-11

Applicant: XILINX, INC.

Inventor： Federico VENINI ,  David TRAN

IPC: G06F30/33 ,  G06F30/323

CPC classification number: G06F30/33 ,  G06F30/323 ,  G06F2119/02

Abstract: Safety mechanisms are embedded into a System on a Chip (SoC) and are operable to detect faults present in the logic circuitry in the SoC. Various types of faults in logic circuitry can occur, for example, a bit stuck at 0 or 1, or a transient or temporary fault due to radiation impacting the SoC. SoC devices are required to meet certain automotive safety integrity standards. The most stringent automotive safety integrity level requires that 90% of random latent faults are detected in all relevant logic, including all safety mechanism. Examples disclosed include hardware based checkers and hardware or software based pattern generation methods that achieve high online fault coverage in safety mechanism circuitry used for functional safety. A hardware based safety mechanism monitors the logic circuitry during operation. Any time the safety mechanism detects any faults in the logic circuitry, a fault notification is propagated to upstream logic.

公开(公告)号：US20240078366A1

公开(公告)日：2024-03-07

申请号：US18139882

申请日：2023-04-26

Applicant: Synopsys, Inc.

Inventor： Eleonora TESTA ,  Luca Gaetano AMARU ,  Patrick Emmanuel VUILLOD

IPC: G06F30/323

CPC classification number: G06F30/323

Abstract: The present disclosure describes systems and methods for adjusting a logic network. The method includes adding, to the logic network, a first redundant node and determining a first adjustment to a first node of the logic network within a transitive fanin of the first redundant node. The method also includes making the first adjustment to the first node based on determining that a first gain based on the first adjustment satisfies a threshold.

公开(公告)号：US20230289502A1

公开(公告)日：2023-09-14

申请号：US18197869

申请日：2023-05-16

Applicant: Battelle Memorial Institute

Inventor： Adam G. Kimura ,  Andrew S. Elliott ,  Daniel A. Perkins

IPC: G06F30/323 ,  G06F30/327

CPC classification number: G06F30/323 ,  G06F30/327 ,  G06F30/33

Abstract: A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.