公开(公告)号：US20210125667A1

公开(公告)日：2021-04-29

申请号：US16667773

申请日：2019-10-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： AMIT SHARMA ,  JOHN PAUL STRACHAN ,  SUHAS KUMAR ,  CATHERINE GRAVES ,  MARTIN FOLTIN ,  CRAIG WARNER

IPC: G11C13/00

Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state. Thus, utility of memristors is enhanced by realizing an optimized write process with decrease latency and improved efficiency.

公开(公告)号：US20210110243A1

公开(公告)日：2021-04-15

申请号：US16598329

申请日：2019-10-10

Applicant: Hewlett Packard Enterprise Development LP

Inventor： CRAIG WARNER ,  Chris Michael Brueggen ,  Eun Sub Lee

IPC: G06N3/063 ,  G06N5/04 ,  G06F9/38 ,  G06F9/52 ,  G06K9/62

Abstract: Systems are methods are provided for implementing a deep learning accelerator system interface (DLASI). The DLASI connects an accelerator having a plurality of inference computation units to a memory of the host computer system during an inference operation. The DLASI allows interoperability between a main memory of a host computer, which uses 64 B cache lines, for example, and inference computation units, such as tiles, which are designed with smaller on-die memory using 16-bit words. The DLASI can include several components that function collectively to provide the interface between the server memory and a plurality of tiles. For example, the DLASI can include: a switch connected to the plurality of tiles; a host interface; a bridge connected to the switch and the host interface; and a deep learning accelerator fabric protocol. The fabric protocol can also implement a pipelining scheme which optimizes throughput of the multiple tiles of the accelerator.