公开(公告)号：US11099958B2

公开(公告)日：2021-08-24

申请号：US16358638

申请日：2019-03-19

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ramesh Chandra Chaurasiya ,  Somasundaram Arunachalam

IPC: G06F11/22 ,  G06F9/30 ,  G06F11/14

Abstract: Examples of instruction generation for validation of processor functionality are described. In an example, a validation instruction to be inserted in an instruction stream is selected. The validation instruction being generated based on an instruction set architecture of a processor-under-test (PUT). It is identified whether a hardware register of the PUT, is available for storing an outcome of execution of the validation instruction by the PUT. The validation instruction is inserted in the instruction stream, in response to identifying that the hardware register is available for storing the outcome. A set of data backup instructions is inserted in the instruction stream, in response to identifying that the hardware register is unavailable for storing the outcome. The set of data backup instructions is to store respective register values of each of the plurality of hardware registers in a primary memory.

公开(公告)号：US11797178B2

公开(公告)日：2023-10-24

申请号：US17377777

申请日：2021-07-16

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ramesh Chandra Chaurasiya ,  Sanish N. Suresh ,  Clarete Riana Crasta ,  Sharad Singhal ,  Porno Shome

IPC: G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0604 ,  G06F3/0631 ,  G06F3/0673 ,  G06F13/28 ,  G06F2213/28

Abstract: A system and method are provided for facilitating efficient management of data structures stored in remote memory. During operation, the system receives a request to allocate memory for a first part in a data structure stored in a remote memory associated with a compute node in a network. The system pre-allocates a buffer in the remote memory for a plurality of parts in the data structure and stores a first local descriptor associated with the buffer in a local worker table stored in a volatile memory of the compute node. The first local descriptor facilitates servicing future access requests to the first and other parts in the data structure. The system stores a first global descriptor for the buffer in a shared global table stored in the remote memory and generates a first reference corresponding to the first part, thereby facilitating faster traversals of the data structure.

公开(公告)号：US20230019758A1

公开(公告)日：2023-01-19

申请号：US17377777

申请日：2021-07-16

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ramesh Chandra Chaurasiya ,  Sanish N. Suresh ,  Clarete Riana Crasta ,  Sharad Singhal ,  Porno Shome

IPC: G06F3/06 ,  G06F13/28

Abstract: A system and method are provided for facilitating efficient management of data structures stored in remote memory. During operation, the system receives a request to allocate memory for a first part in a data structure stored in a remote memory associated with a compute node in a network. The system pre-allocates a buffer in the remote memory for a plurality of parts in the data structure and stores a first local descriptor associated with the buffer in a local worker table stored in a volatile memory of the compute node. The first local descriptor facilitates servicing future access requests to the first and other parts in the data structure. The system stores a first global descriptor for the buffer in a shared global table stored in the remote memory and generates a first reference corresponding to the first part, thereby facilitating faster traversals of the data structure.

公开(公告)号：US20200301795A1

公开(公告)日：2020-09-24

申请号：US16358638

申请日：2019-03-19

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ramesh Chandra Chaurasiya ,  Somasundaram Arunachalam

IPC: G06F11/22 ,  G06F11/14 ,  G06F9/30

Abstract: Examples of instruction generation for validation of processor functionality are described. In an example, a validation instruction to be inserted in an instruction stream is selected. The validation instruction being generated based on an instruction set architecture of a processor-under-test (PUT). It is identified whether a hardware register of the PUT, is available for storing an outcome of execution of the validation instruction by the PUT. The validation instruction is inserted in the instruction stream, in response to identifying that the hardware register is available for storing the outcome. A set of data backup instructions is inserted in the instruction stream, in response to identifying that the hardware register is unavailable for storing the outcome. The set of data backup instructions is to store respective register values of each of the plurality of hardware registers in a primary memory.