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公开(公告)号：US20190250822A1
公开(公告)日：2019-08-15
申请号：US16121086
申请日：2018-09-04
申请人： SK hynix Inc.
发明人： Hyoung Pil CHOI
CPC分类号： G06F3/064 , G06F3/0611 , G06F3/0656 , G06F3/0673 , G06F11/2094 , G06F2201/82
摘要： There are provided a memory controller and a memory system having the same. The memory controller includes: a control processor configured to set groups of memory blocks among memory blocks in a memory device to respective super blocks based on reference values, and store and execute firmware blocks respectively allocated to the super blocks; and a buffer memory configured to store information regarding the super blocks set by the control processor.
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公开(公告)号：US20190243583A1
公开(公告)日：2019-08-08
申请号：US16390031
申请日：2019-04-22
发明人： Akira Koseki , Shuichi Shimizu , Kohji Takano
CPC分类号： G06F3/0673 , G06N5/046
摘要： A method, computer system, and a computer program product for conducting forward reasoning is provided. The present invention may include conducting the forward reasoning, wherein the forward reasoning includes selecting a rule from a plurality of rules stored in a rule base and executing an action, wherein the rule is associated with a condition satisfied by internal states stored in a working memory, and wherein the action is associated with the condition. The present invention may also include detecting the action is creating a one-time object. The present invention may then include conducting the forward reasoning with a first new context in response to the detected one-time object, wherein the one-time object is stored as one of the internal states in the working memory. The present invention may further include deleting the one-time object in response to a completion of the forward reasoning with the first new context.
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公开(公告)号：US20190237133A1
公开(公告)日：2019-08-01
申请号：US16379167
申请日：2019-04-09
发明人： Yanggyoon LOH , Hoyoung SONG , Sangwoong SHIN
IPC分类号： G11C11/406 , G11C11/4096 , G11C11/4091 , G11C11/408 , G06F3/06
CPC分类号： G11C11/40615 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G11C11/40611 , G11C11/40618 , G11C11/4087 , G11C11/4091 , G11C11/4096
摘要： A volatile memory device includes a refresh controller configured to control a hidden refresh operation performed on a first portion of memory cells while a valid operation is performed on a second portion of the memory cells. The volatile memory device is configured to perform a regular refresh operation in response to receiving a refresh command. The refresh controller is configured to generate refresh information using a performance indicator of the hidden refresh operation during a first part of a reference time. The volatile memory device is configured to perform a desired number of the regular refresh operation during a remaining part of the reference time based on the refresh information. The desired number of the regular refresh operation is an integer based on a difference between a target number of refresh operations during the reference time and a count value of the hidden refresh operation during the reference time.
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4.发明申请公开(公告)号：US20190227735A1
公开(公告)日：2019-07-25
申请号：US16371613
申请日：2019-04-01
发明人： Tal Shaked , Omer Gilad , Liat Hod , Eyal Sobol , Einav Zilberstein , Judah Gamliel Hahn
IPC分类号： G06F3/06
CPC分类号： G06F3/0653 , G06F3/0604 , G06F3/0673
摘要： A method and system for visualizing a correlation between host commands and storage system performance are provided. In one embodiment, a method comprises receiving information concerning host operations of a host performed over a time period; receiving information concerning storage system operations of a storage system performed over the time period; and simultaneously displaying both the host operations and the storage system operations over the time period. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
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公开(公告)号：US20190220356A1
公开(公告)日：2019-07-18
申请号：US16369102
申请日：2019-03-29
发明人： Jiajin ZHANG , Matt M.T. YIU , Pak-Ching LEE
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/0644 , G06F3/0673 , G06F11/10 , G06F12/02
摘要： A data processing method is disclosed, and the method includes: encoding a data chunk of a predetermined size, to generate an error-correcting data chunk corresponding to the data chunk, where the data chunk includes a data object, and the data object includes a key, a value, and metadata; and generating a data chunk index and a data object index, where the data chunk index is used to retrieve the data chunk and the error-correcting data chunk corresponding to the data chunk, the data object index is used to retrieve the data object in the data chunk, and each data object index is used to retrieve a unique data object.
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公开(公告)号：US20190220352A1
公开(公告)日：2019-07-18
申请号：US16030025
申请日：2018-07-09
发明人： Jeong Yun Cha , June Hyun Park
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/0659 , G06F3/0673 , G11C11/409 , G11C29/52
摘要： A memory device comprises a plurality of memory banks, each of the plurality of memory banks includes a bank array having a plurality of memory cells, a row decoder selecting at least one of word lines connecting to the plurality of memory cells, and a column decoder selecting at least one of bit lines connecting to the plurality of memory cells, and each of the plurality of memory cells includes a capacitor and a transistor, a write circuit configured to store input data received at the memory device from a test device in the bank array, a read circuit configured to generate output data based on reading data stored in the bank array, a parity data management circuit configured to generate first parity data having a size smaller than the input data using the input data, generate second parity data having a size smaller than the output data using the output data, and generate third parity data using the first parity data and the second parity data, and an output circuit configured to output at least one instance of data of the first parity data, the second parity data, and the third parity data as verification data, in response to a receipt of a request from the test device at the memory device.
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公开(公告)号：US20190220272A1
公开(公告)日：2019-07-18
申请号：US16362325
申请日：2019-03-22
发明人： Christopher Kevan LOWE , Gengshi WU
CPC分类号： G06F8/658 , G06F3/0604 , G06F3/065 , G06F3/0659 , G06F3/0673 , G06F8/654
摘要： A patch generator for generating a patch that expresses a series of updates to a source image that will transform the source image into a target image. The patch generator compares sections of the target image, in turn, with respective versions of the source image. The patch generator generates the series of updates for the patch in dependence on the comparisons between the sections of the target image and the respective versions of the source image. Comparing each section of the target image with versions of the source image that are expected to be stored by the device during the process of implementing the patch allows the possibility that the device could change the source image in its memory while it implements the patch.
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公开(公告)号：US20190220199A1
公开(公告)日：2019-07-18
申请号：US16363587
申请日：2019-03-25
CPC分类号： G06F3/0607 , G06F3/0629 , G06F3/0658 , G06F3/0673 , G06F9/3009 , G06F9/3851 , G06F9/5016 , G06F9/542 , G06F9/544 , G06F12/1081 , G06F13/28 , G06F2212/251
摘要： A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.
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公开(公告)号：US20190215352A1
公开(公告)日：2019-07-11
申请号：US16352509
申请日：2019-03-13
发明人： Chuanshuai Yu , Chengwei Zhang , Linbo Xu
IPC分类号： H04L29/06 , H04L12/801 , G06F3/06
CPC分类号： H04L65/602 , G06F3/0608 , G06F3/0641 , G06F3/0673 , G06F17/3033 , G06F17/3053 , H04L47/10
摘要： Embodiments of the present invention provide a method for searching for a data stream dividing point based on a server. In the embodiments of the present invention, a data stream dividing point is searched for by determining whether at least a part of data in a window of M windows meets a preset condition, and when the at least a part of data in the window does not meet the preset condition, a length of N*U is skipped, so as to obtain a next potential dividing point, thereby improving efficiency of searching for a data stream dividing point.
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公开(公告)号：US20190213075A1
公开(公告)日：2019-07-11
申请号：US16152170
申请日：2018-10-04
申请人： SK hynix Inc.
发明人： Do Hun KIM
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/0659 , G06F3/0673
摘要： A memory system may include a first memory and a second memory. The second memory may have a characteristic different from the first memory. The memory system may include a data attribute determination circuit configured to determine an attribute on data to be stored. The memory system may include a memory selection circuit configured to selectively store parity information on the data in the first memory or the second memory, based on the attribute of the data.
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