公开(公告)号：US08963583B2

公开(公告)日：2015-02-24

申请号：US14185296

申请日：2014-02-20

Applicant: HiDeep Inc

Inventor： Donggu Im ,  Seunghyun Park ,  Bonkee Kim ,  Youngho Cho

IPC: H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/0185

Abstract: Disclosed is a voltage level converter that includes: a first conversion unit which receives at least one input signal of a logic 1 signal and a logic 0 signal from a signal input terminal and converts the signal; a second conversion unit and a third conversion unit which alternately output a logic −1 signal and the logic 1 signal respectively in accordance with the input signal; a fourth conversion unit and a fifth conversion unit which alternately output the logic −1 signal and the logic 0 signal respectively in accordance with the input signal; and a latch which has a complementary characteristic in which if a first transistor becomes an on-state, then a second transistor becomes an off-state in accordance with the input signal, and performs a positive feedback operation. A drain output of the first transistor is input to the fourth conversion unit. A drain output of the second transistor is input to the fifth conversion unit.

Abstract translation: 公开了一种电压电平转换器，包括：第一转换单元，其从信号输入端接收至少一个逻辑1信号的输入信号和逻辑0信号，并转换该信号; 第二转换单元和第三转换单元，其根据输入信号分别交替地输出逻辑-1信号和逻辑1信号; 第四转换单元和第五转换单元，其根据输入信号分别交替地输出逻辑-1信号和逻辑0信号; 以及具有互补特性的锁存器，其中如果第一晶体管变为导通状态，则第二晶体管根据输入信号变为截止状态，并且执行正反馈操作。 第一晶体管的漏极输出被输入到第四转换单元。 第二晶体管的漏极输出被输入到第五转换单元。

公开(公告)号：US20140240002A1

公开(公告)日：2014-08-28

申请号：US14185296

申请日：2014-02-20

Applicant: HiDeep Inc

Inventor： Donggu IM ,  Seunghyun Park ,  Bonkee Kim ,  Youngho Cho

IPC: H03K19/0185

CPC classification number: H03K19/0185

Abstract: Disclosed is a voltage level converter that includes: a first conversion unit which receives at least one input signal of a logic 1 signal and a logic 0 signal from a signal input terminal and converts the signal; a second conversion unit and a third conversion unit which alternately output a logic −1 signal and the logic 1 signal respectively in accordance with the input signal; a fourth conversion unit and a fifth conversion unit which alternately output the logic −1 signal and the logic 0 signal respectively in accordance with the input signal; and a latch which has a complementary characteristic in which if a first transistor becomes an on-state, then a second transistor becomes an off-state in accordance with the input signal, and performs a positive feedback operation. A drain output of the first transistor is input to the fourth conversion unit. A drain output of the second transistor is input to the fifth conversion unit.

Abstract translation: 公开了一种电压电平转换器，包括：第一转换单元，其从信号输入端接收至少一个逻辑1信号的输入信号和逻辑0信号，并转换该信号; 第二转换单元和第三转换单元，其根据输入信号分别交替地输出逻辑-1信号和逻辑1信号; 第四转换单元和第五转换单元，其根据输入信号分别交替地输出逻辑-1信号和逻辑0信号; 以及具有互补特性的锁存器，其中如果第一晶体管变为导通状态，则第二晶体管根据输入信号变为截止状态，并且执行正反馈操作。 第一晶体管的漏极输出被输入到第四转换单元。 第二晶体管的漏极输出被输入到第五转换单元。