公开(公告)号：US09208087B2

公开(公告)日：2015-12-08

申请号：US13687955

申请日：2012-11-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zixue Bi ,  Hua Wei ,  Chunlei Fan

IPC: G06F12/08 ,  G06F12/12 ,  H04L29/06

CPC classification number: G06F12/0806 ,  G06F12/0804 ,  G06F12/121 ,  G06F2212/174 ,  H04L69/14

Abstract: The present invention discloses a data caching method and apparatus, and relates to the field of network applications. The method includes: receiving a first data request; writing target data in the first data request into an on-chip Cache, and counting a storage time of the target data in the on-chip cache; enabling a delay expiry identifier of the target data when the storage time of the target data in the Cache reaches a preset delay time; and releasing the target data when the delay expiry identifier of the target data is in an enabled state and processing of the target data is complete.

Abstract translation: 本发明公开了一种数据缓存方法和装置，涉及到网络应用领域。 该方法包括：接收第一数据请求; 将所述第一数据请求中的目标数据写入到片上高速缓存中，并对所述片上高速缓存中的目标数据的存储时间进行计数; 当Cache中的目标数据的存储时间达到预设的延迟时间时，启用目标数据的延迟到期标识符; 并且当目标数据的延迟到期标识符处于使能状态并且目标数据的处理完成时释放目标数据。

公开(公告)号：US20140089633A1

公开(公告)日：2014-03-27

申请号：US14092213

申请日：2013-11-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Chunlei Fan ,  Wenhua Du ,  Zixue Bi

IPC: G06F12/06

CPC classification number: G06F12/063 ,  G06F12/0223 ,  G06F12/1408 ,  G06F17/15 ,  G06F17/156 ,  G06F21/12 ,  G06F21/14

Abstract: The present invention relates to the field of communication technologies and discloses a method and an apparatus for encoding a data address, so that attacks can be effectively prevented and resources and costs required to handle a bank conflict are reduced. In solutions provided by embodiments of the present invention, an exclusive-OR operation is performed on one or more bits of a received uncoded address by using multiple preset transform polynomials; and an encoded address is obtained according to a result of the exclusive-OR operation. The solutions provided by the embodiments of the present invention are applicable to designs that require a large-capacity DRAM, high performance and high reliability, and have an anti-attack demand.

Abstract translation: 本发明涉及通信技术领域，并且公开了一种用于对数据地址进行编码的方法和装置，从而可以有效地防止攻击，减少了处理银行冲突所需的资源和成本。 在本发明实施例提供的解决方案中，通过使用多个预设变换多项式对接收到的未编码地址的一个或多个比特执行异或运算; 并且根据异或运算的结果获得编码地址。 本发明实施例提供的解决方案适用于需要大容量DRAM，高性能和高可靠性并具有抗攻击需求的设计。

公开(公告)号：US09442845B2

公开(公告)日：2016-09-13

申请号：US14092213

申请日：2013-11-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Chunlei Fan ,  Wenhua Du ,  Zixue Bi

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F17/15 ,  G06F12/06 ,  G06F12/02 ,  G06F21/12 ,  G06F21/14 ,  G06F12/14

CPC classification number: G06F12/063 ,  G06F12/0223 ,  G06F12/1408 ,  G06F17/15 ,  G06F17/156 ,  G06F21/12 ,  G06F21/14

Abstract: The present invention relates to the field of communication technologies and discloses a method and an apparatus for encoding a data address, so that attacks can be effectively prevented and resources and costs required to handle a bank conflict are reduced. In solutions provided by embodiments of the present invention, an exclusive-OR operation is performed on one or more bits of a received uncoded address by using multiple preset transform polynomials; and an encoded address is obtained according to a result of the exclusive-OR operation. The solutions provided by the embodiments of the present invention are applicable to designs that require a large-capacity DRAM, high performance and high reliability, and have an anti-attack demand.

Abstract translation: 本发明涉及通信技术领域，并且公开了一种用于对数据地址进行编码的方法和装置，从而可以有效地防止攻击，减少了处理银行冲突所需的资源和成本。 在本发明实施例提供的解决方案中，通过使用多个预设变换多项式对接收到的未编码地址的一个或多个比特执行异或运算; 并且根据异或运算的结果获得编码地址。 本发明实施例提供的解决方案适用于需要大容量DRAM，高性能和高可靠性并具有抗攻击需求的设计。

公开(公告)号：US09122411B2

公开(公告)日：2015-09-01

申请号：US14143101

申请日：2013-12-30

Applicant: Huawei Technologies Co., Ltd.

Inventor： Chunlei Fan ,  Zhuo Chen ,  Renjie Qu

IPC: G06F5/06

CPC classification number: G06F5/065 ,  G06F5/06

Abstract: Embodiments of the present invention relate to a signal order-preserving method and apparatus. When data of a request signal that comes from a corresponding first upstream device is written into a first first input first output (FIFO) memory, invalid data is written into a second FIFO memory corresponding to a second upstream device in a same clock cycle; and the data of the request signal is read from the first FIFO memory, the invalid data is read from the second FIFO memory, the invalid data is discarded, and the data of the request signal is conveyed to a downstream device. Through the signal order-preserving method and apparatus in the embodiments of the present invention, the coupling extent between devices on which there is an order-preserving requirement is reduced while signal order-preserving is achieved.

Abstract translation: 本发明的实施例涉及信号顺序保存方法和装置。 当来自相应的第一上游设备的请求信号的数据被写入到第一第一输入第一输出（FIFO）存储器中时，无效数据以相同的时钟周期写入对应于第二上游设备的第二FIFO存储器中; 并且从第一FIFO存储器读取请求信号的数据，从第二FIFO存储器读取无效数据，丢弃无效数据，并将请求信号的数据传送到下游设备。 通过本发明的实施例中的信号顺序保存方法和装置，减少了维持信号顺序的装置之间的耦合范围。

公开(公告)号：US20140115201A1

公开(公告)日：2014-04-24

申请号：US14143101

申请日：2013-12-30

Applicant: Huawei Technologies Co., Ltd.

Inventor： Chunlei Fan ,  Zhuo Chen ,  Renjie Qu

IPC: G06F5/06

CPC classification number: G06F5/065 ,  G06F5/06

Abstract: Embodiments of the present invention relate to a signal order-preserving method and apparatus. When data of a request signal that comes from a corresponding first upstream device is written into a first first input first output (FIFO) memory, invalid data is written into a second FIFO memory corresponding to a second upstream device in a same clock cycle; and the data of the request signal is read from the first FIFO memory, the invalid data is read from the second FIFO memory, the invalid data is discarded, and the data of the request signal is conveyed to a downstream device. Through the signal order-preserving method and apparatus in the embodiments of the present invention, the coupling extent between devices on which there is an order-preserving requirement is reduced while signal order-preserving is achieved.

Abstract translation: 本发明的实施例涉及信号顺序保存方法和装置。 当来自相应的第一上游设备的请求信号的数据被写入到第一第一输入第一输出（FIFO）存储器中时，无效数据以相同的时钟周期写入对应于第二上游设备的第二FIFO存储器中; 并且从第一FIFO存储器读取请求信号的数据，从第二FIFO存储器读取无效数据，丢弃无效数据，并将请求信号的数据传送到下游设备。 通过本发明的实施例中的信号顺序保存方法和装置，减少了维持信号顺序的装置之间的耦合范围。