公开(公告)号：US20160308633A1

公开(公告)日：2016-10-20

申请号：US15190881

申请日：2016-06-23

Applicant: Huawei Technologies Co., Ltd.

Inventor： Fan Liu ,  Liankui Lin ,  Xin Lv

IPC: H04J3/06 ,  H04L7/033

CPC classification number: H04J3/0697 ,  H04L7/0331 ,  H04L12/4641

Abstract: The present invention discloses a clock synchronization method in a multi-clock domain, a line card, and an Ethernet device. The method includes: acquiring, by a sending line card, M clock frequency differences that are determined by a receiving line card and that are of M uplink interfaces corresponding to M downlink interfaces on the sending line card, where the M uplink interfaces are uplink interfaces on the receiving line card, and M is a positive integer; and adjusting, by the sending line card by using each clock frequency difference of the M clock frequency differences of the M uplink interfaces and based on a correspondence between the M downlink interfaces and the M uplink interfaces, a transmit clock of an interface corresponding to the clock frequency difference.

Abstract translation: 本发明公开了一种多时钟域中的时钟同步方法，线路卡和以太网装置。 该方法包括：通过发送线路卡获取由接收线路卡确定的M个时钟频率差，M个上行链路接口对应于发送线路卡上的M个下行链路接口，其中M个上行链路接口是上行链路接口 在接收线卡上，M是正整数; 并且通过使用M个上行链路接口的M个时钟频率差的每个时钟频率差异，并且基于M个下行链路接口和M个上行链路接口之间的对应关系来调整发送线路卡，对应于 时钟频率差。