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公开(公告)号:US20210294852A1
公开(公告)日:2021-09-23
申请号:US17338218
申请日:2021-06-03
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor: Chong LI , Zhen ZHANG , Kun MAO
IPC: G06F16/901 , G06F3/06
Abstract: A data processing method and apparatus are described. The data processing apparatus obtains an input tensor corresponding to input data. The data processing apparatus determines M1 first-type tensor blocks and M2 second-type tensor blocks. P processing units in the data processing apparatus process the M tensor blocks concurrently. In a first time period, all of the tensor blocks that are processed concurrently by the P processing units are first-type tensor blocks. In a second time period, all of the tensor blocks that are processed concurrently by the P processing units are second-type tensor blocks.
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公开(公告)号:US20240282109A1
公开(公告)日:2024-08-22
申请号:US18652265
申请日:2024-05-01
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor: Chong LI , Zhen ZHANG , Kun MAO
CPC classification number: G06V20/46 , G06F3/0604 , G06F3/064 , G06F3/0673 , G06F16/9017 , G06V10/50 , G06V10/94 , G06V10/28
Abstract: A data processing method and apparatus are described. The data processing apparatus obtains an input tensor corresponding to input data. The data processing apparatus determines M1 first-type tensor blocks and M2 second-type tensor blocks. P processing units in the data processing apparatus process the M tensor blocks concurrently. In a first time period, all of the tensor blocks that are processed concurrently by the P processing units are first-type tensor blocks. In a second time period, all of the tensor blocks that are processed concurrently by the P processing units are second-type tensor blocks.
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公开(公告)号:US20230236888A1
公开(公告)日:2023-07-27
申请号:US18127300
申请日:2023-03-28
Applicant: Huawei Technologies Co., Ltd.
Inventor: Zhen ZHANG , Ioannis LAMPROU , Javier DE JUAN , Chang LIU
IPC: G06F9/50
CPC classification number: G06F9/5016 , G06F9/5033
Abstract: This application provides a memory allocation method. The method includes: obtaining a computation graph corresponding to a neural network; sequentially allocating memory space to M pieces of tensor data based on a sorting result of the M pieces of tensor data, where if at least a part of the allocated memory space can be reused for one of the M pieces of tensor data, the at least a part of the memory space that can be reused for the tensor data is allocated to the tensor data, the allocated memory space is memory space that has been allocated to the M pieces of tensor data before the tensor data, the sorting result indicates a sequence of allocating memory space to the M pieces of tensor data, and the sorting result is related to information about each of the M pieces of tensor data.
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公开(公告)号:US20240045716A1
公开(公告)日:2024-02-08
申请号:US18478587
申请日:2023-09-29
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor: Cedric Bastoul , Zhen ZHANG
CPC classification number: G06F9/4881 , G06F9/3838
Abstract: A data processing apparatus is provided, comprising a processing circuitry configured to implement a scheduling constraints injection entity configured to, based on one or more scheduling constraints, adapt a polyhedral intermediate representation of an input code for obtaining an adapted polyhedral intermediate representation of the input code. The processing circuitry is further configured to implement a polyhedral scheduler configured to generate, based on the adapted polyhedral intermediate representation of the input code, a scheduled polyhedral intermediate representation of the input code. The scheduling constraints injection entity is further configured to, based on the one or more scheduling constraints, adjust the polyhedral scheduler. Moreover, a corresponding data processing method is disclosed.
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