公开(公告)号：US3577128A

公开(公告)日：1971-05-04

申请号：US3577128D

申请日：1969-01-14

Applicant: IBM

Inventor： CRISCIMAGNA TONY N ,  FOURNIER ROBERT J

IPC: G06F13/10 ,  G04G7/00 ,  G06F1/10 ,  G06F1/12 ,  G06F3/06 ,  H04L7/033 ,  H04L7/04 ,  H03K3/64

CPC classification number: G06F1/10 ,  G04G7/00

Abstract: In a data processing system, apparatus for synchronizing a slave clock in an input/output device with a master clock in a central processing unit. A set of clock signals from a CPU are received in parallel, converted to serial and pulses are generated in response to the leading and trailing edge of each of the series of signals. The series of pulses is then delayed and shaped to drive a slaved I/O clock. A delay line is adjusted so that the total equivalent system delay is equal to an integral number of CPU pulse durations.

公开(公告)号：US3334304A

公开(公告)日：1967-08-01

申请号：US43607865

申请日：1965-03-01

Applicant: IBM

Inventor： FOURNIER ROBERT J ,  WINTER LEONARD F

IPC: G09G1/10

CPC classification number: G09G1/10