Binary adder circuit
    1.
    发明授权
    Binary adder circuit 失效
    二进制电路

    公开(公告)号:US3902055A

    公开(公告)日:1975-08-26

    申请号:US44913374

    申请日:1974-03-07

    Applicant: IBM

    CPC classification number: G06F7/506 G06F7/501

    Abstract: An improvement in binary adder circuits based on a new Boolean algorithm is disclosed. The arrangement permits calculation of the carry from the logical combination of the addend, the EXCLUSIVE OR of the addend and the augend, and the carry of the next preceding stage. The circuit is readily implemented in NOR logic and has particular application in large scale integrated circuits (LSI).

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