公开(公告)号：US20020129224A1

公开(公告)日：2002-09-12

申请号：US09683351

申请日：2001-12-18

Applicant: IBM

Inventor： Petra Leber ,  Jens Leenstra ,  Wolfram Sauer ,  Dieter Wendel

IPC: G06F009/00

CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: A method for operating a processor having an architecture of a larger bitlength with a program comprising instructions compiled to produce instruction results of at least one smaller bitlength having the steps of detecting when in program order a first smaller bitlength instruction is to be dispatched which does not have a target register address as one of its sources, and adding a so_extract_instruction into an instruction stream before the smaller bitlength instruction. The extract instruction includes the steps of dispatching the extract instruction together with the following smaller bitlength instruction from an instruction queue into a Reservation Station, issuing the extract instruction to an Instruction Execution Unit (IEU) as soon as all source operand data is available and an IEU is available according to respective issue scheme, executing the extract instruction by an available IEU, setting an indication that the result of the instruction needs to be written into the result field of the instruction following the extract instruction, and writing the extract instruction result into the result field of the first instruction, and into all fields of operands being dependent of the first instruction.

Abstract translation: 一种用于操作具有较大位长度的架构的处理器的方法，所述程序包括编译为产生至少一个较小位长度的指令结果的指令的程序，所述指令结果具有以下步骤：在程序顺序中检测何时将发送第一较小位长指令， 将目标寄存器地址作为其源之一，并在较小的比特长指令之前将so_extract_instruction添加到指令流中。 提取指令包括以下步骤：将提取指令与以下较小的比特长指令一起从指令队列发送到预留站，一旦所有源操作数数据可用，就将提取指令发送到指令执行单元（IEU），并且 IEU根据各自的发行方案可用，通过可用的IEU执行提取指令，将提示结果的指示需要写入到提取指令之后的指令的结果字段中，并将提取指令结果写入 第一条指令的结果字段，以及依赖于第一条指令的操作数的所有字段。