公开(公告)号：US20030208672A1

公开(公告)日：2003-11-06

申请号：US09683383

申请日：2001-12-20

Applicant: IBM

Inventor： Jens Leenstra ,  Antje Mueller ,  Juergen Pille ,  Dieter Wendel

IPC: G06F009/30 ,  G06F009/40 ,  G06F015/00

CPC classification number: G06F9/3873 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

Abstract: A method and system for operating a high frequency outprocessor with increased pipeline length. A new scheme is disclosed to reduce the pipeline by the detection and exploitation of so called nullno_dependencynull for an instruction. A nullno dependencynull signal tells that all required source data is available for the instruction at least one cycle before the source data valid bit(s) are inserted into the issue queue. Therefore, one or more stages of the pipeline are bypassed. Bypassing the pipeline stages for this nullno dependencynull conditions is especially important since a no dependency is found when the queue is empty. Furthermore, this bypass is very effective when the queue is relatively empty. Therefore, introducing such a bypass reduces effectively the performance drawback of a longer pipeline.

Abstract translation: 一种用于操作具有增加的管道长度的高频外部处理器的方法和系统。 公开了一种新方案，通过对指令的所谓“不相关”的检测和利用来减少流水线。 “无依赖”信号指示在将源数据有效位插入到发出队列之前至少一个周期，所有必需的源数据可用于该指令。 因此，管道的一个或多个阶段被绕过。 绕过这个“不依赖”条件的流水线阶段特别重要，因为当队列为空时，找不到依赖关系。 此外，当队列相对空时，此旁路是非常有效的。 因此，引入这样的旁路有效地降低了更长管道的性能缺陷。

公开(公告)号：US20020129224A1

公开(公告)日：2002-09-12

申请号：US09683351

申请日：2001-12-18

Applicant: IBM

Inventor： Petra Leber ,  Jens Leenstra ,  Wolfram Sauer ,  Dieter Wendel

IPC: G06F009/00

CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: A method for operating a processor having an architecture of a larger bitlength with a program comprising instructions compiled to produce instruction results of at least one smaller bitlength having the steps of detecting when in program order a first smaller bitlength instruction is to be dispatched which does not have a target register address as one of its sources, and adding a so_extract_instruction into an instruction stream before the smaller bitlength instruction. The extract instruction includes the steps of dispatching the extract instruction together with the following smaller bitlength instruction from an instruction queue into a Reservation Station, issuing the extract instruction to an Instruction Execution Unit (IEU) as soon as all source operand data is available and an IEU is available according to respective issue scheme, executing the extract instruction by an available IEU, setting an indication that the result of the instruction needs to be written into the result field of the instruction following the extract instruction, and writing the extract instruction result into the result field of the first instruction, and into all fields of operands being dependent of the first instruction.

Abstract translation: 一种用于操作具有较大位长度的架构的处理器的方法，所述程序包括编译为产生至少一个较小位长度的指令结果的指令的程序，所述指令结果具有以下步骤：在程序顺序中检测何时将发送第一较小位长指令， 将目标寄存器地址作为其源之一，并在较小的比特长指令之前将so_extract_instruction添加到指令流中。 提取指令包括以下步骤：将提取指令与以下较小的比特长指令一起从指令队列发送到预留站，一旦所有源操作数数据可用，就将提取指令发送到指令执行单元（IEU），并且 IEU根据各自的发行方案可用，通过可用的IEU执行提取指令，将提示结果的指示需要写入到提取指令之后的指令的结果字段中，并将提取指令结果写入 第一条指令的结果字段，以及依赖于第一条指令的操作数的所有字段。

公开(公告)号：US20040246027A1

公开(公告)日：2004-12-09

申请号：US10455170

申请日：2003-06-05

Applicant: IBM Corporation

Inventor： Sang Hoo Dhong ,  Joel Abraham Silberman ,  Osamu Takahashi ,  James Douglas Warnock ,  Dieter Wendel

IPC: H03K019/00

CPC classification number: G06F1/10

Abstract: Several local clock buffers are disclosed, each including an input section and an output section. The input sections are substantially identical, and include control logic and gating logic. The control logic produces a gating signal dependent upon multiple control signals and a time-delayed global clock signal. The gating logic produces an intermediate clock signal dependent upon the global clock signal and the gating signal. The output section produces at least one local clock signal dependent upon the intermediate clock signal. In one embodiment, the output section produces a first local clock signal dependent upon the intermediate clock signal and a second local clock signal dependent upon the first local clock signal. In another embodiment, the gating logic produces the intermediate clock signal dependent upon the global clock and gating signals and a feedback signal. The output section produces the feedback signal and one or more local clock signals.

公开(公告)号：US20020083304A1

公开(公告)日：2002-06-27

申请号：US09683391

申请日：2001-12-20

Applicant: IBM

Inventor： Jens Leenstra ,  Dieter Wendel

IPC: G06F009/30

CPC classification number: G06F9/3838 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: An improved method and system for operating an out of order processor at a high frequency enabled by an increased pipeline length. It is proposed to shorten the pipeline by a considerable number of stages by accepting that a write after read conflict may occur, when directly after renaming, during the nullread ROBnull pipeline stage, all the information (tag, validity and data) is read from an Reorder Buffer ROB entry, and is next written, in a following pipeline stage nullwrite RSnull, into a reservation station (RS) entry. In order to assure the correctness of processing in particular in cases of dependencies, e.g., write after read conflicts a separate inventional add in logic covers these cases. The logic detects the write after read conflict case of an Instructional Execution Unit (IEU) writing into the particular entry that is selected by the renaming logic during nullread ROBnull. Then, a separate issue process selects the entries for which a conflict is reported and writes the data into the respective entry of the RS. This increases performance because those conflict cases are rather seldom compared to the broad majority of instructions to be found in a statistically determined average instruction flow.

Abstract translation: 一种改进的方法和系统，用于通过增加的流水线长度在高频下操作无序处理器。 建议通过接受在读取冲突之后写入，直接在重命名之后，在“读取ROB”流水线阶段期间，可以读取所有信息（标签，有效性和数据），缩短流水线 来自重排序缓冲器ROB条目，并且在下一个流水线级“写入RS”中被写入保留站（RS）条目。 为了确保处理的正确性，特别是在依赖性的情况下，例如在读取冲突之后写入，单独的发明逻辑将覆盖这些情况。 该逻辑检测指令执行单元（IEU）写入读写冲突之后的写入到在“读取ROB”期间由重命名逻辑选择的特定条目。 然后，单独的问题过程选择报告冲突的条目，并将数据写入RS的相应条目。 这增加了性能，因为这些冲突案例与在统计确定的平均指令流程中找到的大多数指令相比很少。