公开(公告)号：US10559677B2

公开(公告)日：2020-02-11

申请号：US15353952

申请日：2016-11-17

Applicant: IMEC VZW

Inventor： Shuzhen You ,  Niels Posthuma

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10

Abstract: The disclosure relates to a method of fabricating an enhancement mode Group III-nitride HEMT device and a Group III-nitride structure fabricated therefrom. One example embodiment is a method for fabricating an enhancement mode Group III-nitride HEMT device. The method includes providing a structure. The structure includes a substrate having a main surface. The structure also includes a layer stack overlying the main surface. Each layer of the layer stack includes a Group III-nitride material. The structure further includes a capping layer on the layer stack. The method also includes forming a recessed gate region by removing, in a gate region, at least the capping layer by performing an etch process, thereby exposing a top surface of an upper layer of the layer stack. The method further includes forming a p-type doped GaN layer in the recessed gate region and on the capping layer by performing a non-selective deposition process.

公开(公告)号：US20170179272A1

公开(公告)日：2017-06-22

申请号：US15353952

申请日：2016-11-17

Applicant: IMEC VZW

Inventor： Shuzhen You ,  Niels Posthuma

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/423 ,  H01L21/306 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66

Abstract: The disclosure relates to a method of fabricating an enhancement mode Group III-nitride HEMT device and a Group III-nitride structure fabricated therefrom. One example embodiment is a method for fabricating an enhancement mode Group III-nitride HEMT device. The method includes providing a structure. The structure includes a substrate having a main surface. The structure also includes a layer stack overlying the main surface. Each layer of the layer stack includes a Group III-nitride material. The structure further includes a capping layer on the layer stack. The method also includes forming a recessed gate region by removing, in a gate region, at least the capping layer by performing an etch process, thereby exposing a top surface of an upper layer of the layer stack. The method further includes forming a p-type doped GaN layer in the recessed gate region and on the capping layer by performing a non-selective deposition process.

公开(公告)号：US20160163695A1

公开(公告)日：2016-06-09

申请号：US14963650

申请日：2015-12-09

Applicant: IMEC VZW

Inventor： Stefaan Decoutere ,  Niels Posthuma ,  Shuzhen You

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/761 ,  H01L21/22 ,  H01L29/778 ,  H01L21/74

CPC classification number: H01L27/0629 ,  H01L21/761 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/1075 ,  H01L29/7786

Abstract: An integrated circuit comprising a first III-N transistor having a source region and a second III-N transistor having a source region, both transistors being monolithically integrated on a common silicon substrate of a first doping type and separated from each-other by an isolation region, the substrate comprising underneath the first transistor a well of a first doping type electrically connected to the source region of the first transistor and comprising underneath the second transistor a well of a second doping type electrically connected to the source region of the second transistor, thereby forming a junction diode in the substrate between the sources of the first and the second transistor.

Abstract translation: 一种集成电路，包括具有源极区的第一III-N晶体管和具有源极区的第二III-N晶体管，两个晶体管单片集成在第一掺杂类型的公共硅衬底上并且通过隔离彼此分离 所述衬底包括在所述第一晶体管下方的第一掺杂类型的阱，所述阱的第一掺杂类型电连接到所述第一晶体管的源极区，并且在所述第二晶体管的下方包括电连接到所述第二晶体管的源极区的第二掺杂型阱， 从而在第一和第二晶体管的源极之间的衬底中形成结二极管。