公开(公告)号：US12002680B2

公开(公告)日：2024-06-04

申请号：US17345229

申请日：2021-06-11

Applicant: IMEC VZW

Inventor： Niels Posthuma ,  Stefaan Decoutere

IPC: H01L21/285 ,  H01L21/3213 ,  H01L29/20 ,  H01L29/423 ,  H01L29/47 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/28581 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method includes providing a semiconductor structure including: a substrate; a layer stack with each layer of the layer stack including a Group III-nitride material; and a p-type doped GaN layer on the layer stack. The method also includes providing, on the GaN layer, a metal bi-layer including a first metal layer in contact with GaN layer and a second metal layer on the first metal layer and having a lower sheet resistance than the first metal layer. The method also includes performing a patterning process upon the metal bi-layer and the p-type doped GaN layer such that a first periphery of the first metal layer is aligned to a second periphery of the second metal layer and such that a first cross section of the metal bi-layer is smaller than a second cross section of the GaN layer parallel to the first cross section.

公开(公告)号：US20170179272A1

公开(公告)日：2017-06-22

申请号：US15353952

申请日：2016-11-17

Applicant: IMEC VZW

Inventor： Shuzhen You ,  Niels Posthuma

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/423 ,  H01L21/306 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66

Abstract: The disclosure relates to a method of fabricating an enhancement mode Group III-nitride HEMT device and a Group III-nitride structure fabricated therefrom. One example embodiment is a method for fabricating an enhancement mode Group III-nitride HEMT device. The method includes providing a structure. The structure includes a substrate having a main surface. The structure also includes a layer stack overlying the main surface. Each layer of the layer stack includes a Group III-nitride material. The structure further includes a capping layer on the layer stack. The method also includes forming a recessed gate region by removing, in a gate region, at least the capping layer by performing an etch process, thereby exposing a top surface of an upper layer of the layer stack. The method further includes forming a p-type doped GaN layer in the recessed gate region and on the capping layer by performing a non-selective deposition process.

公开(公告)号：US10559677B2

公开(公告)日：2020-02-11

申请号：US15353952

申请日：2016-11-17

Applicant: IMEC VZW

Inventor： Shuzhen You ,  Niels Posthuma

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10

Abstract: The disclosure relates to a method of fabricating an enhancement mode Group III-nitride HEMT device and a Group III-nitride structure fabricated therefrom. One example embodiment is a method for fabricating an enhancement mode Group III-nitride HEMT device. The method includes providing a structure. The structure includes a substrate having a main surface. The structure also includes a layer stack overlying the main surface. Each layer of the layer stack includes a Group III-nitride material. The structure further includes a capping layer on the layer stack. The method also includes forming a recessed gate region by removing, in a gate region, at least the capping layer by performing an etch process, thereby exposing a top surface of an upper layer of the layer stack. The method further includes forming a p-type doped GaN layer in the recessed gate region and on the capping layer by performing a non-selective deposition process.

公开(公告)号：US20220181159A1

公开(公告)日：2022-06-09

申请号：US17345229

申请日：2021-06-11

Applicant: IMEC VZW

Inventor： Niels Posthuma ,  Stefaan Decoutere

IPC: H01L21/285 ,  H01L29/20 ,  H01L29/423 ,  H01L29/47 ,  H01L29/778 ,  H01L21/3213 ,  H01L29/66

Abstract: A method includes providing a semiconductor structure including: a substrate; a layer stack with each layer of the layer stack including a Group III-nitride material; and a p-type doped GaN layer on the layer stack. The method also includes providing, on the GaN layer, a metal bi-layer including a first metal layer in contact with GaN layer and a second metal layer on the first metal layer and having a lower sheet resistance than the first metal layer. The method also includes performing a patterning process upon the metal bi-layer and the p-type doped GaN layer such that a first periphery of the first metal layer is aligned to a second periphery of the second metal layer and such that a first cross section of the metal bi-layer is smaller than a second cross section of the GaN layer parallel to the first cross section.

公开(公告)号：US11114537B2

公开(公告)日：2021-09-07

申请号：US16748192

申请日：2020-01-21

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Niels Posthuma ,  Brice De Jaeger

IPC: H01L29/47 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L21/285 ,  H01L21/3213

Abstract: Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.

公开(公告)号：US20200235218A1

公开(公告)日：2020-07-23

申请号：US16748192

申请日：2020-01-21

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Niels Posthuma ,  Brice De Jaeger

IPC: H01L29/47 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/3213 ,  H01L21/285 ,  H01L29/66

Abstract: Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.

公开(公告)号：US20160163695A1

公开(公告)日：2016-06-09

申请号：US14963650

申请日：2015-12-09

Applicant: IMEC VZW

Inventor： Stefaan Decoutere ,  Niels Posthuma ,  Shuzhen You

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/761 ,  H01L21/22 ,  H01L29/778 ,  H01L21/74

CPC classification number: H01L27/0629 ,  H01L21/761 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/1075 ,  H01L29/7786

Abstract: An integrated circuit comprising a first III-N transistor having a source region and a second III-N transistor having a source region, both transistors being monolithically integrated on a common silicon substrate of a first doping type and separated from each-other by an isolation region, the substrate comprising underneath the first transistor a well of a first doping type electrically connected to the source region of the first transistor and comprising underneath the second transistor a well of a second doping type electrically connected to the source region of the second transistor, thereby forming a junction diode in the substrate between the sources of the first and the second transistor.

Abstract translation: 一种集成电路，包括具有源极区的第一III-N晶体管和具有源极区的第二III-N晶体管，两个晶体管单片集成在第一掺杂类型的公共硅衬底上并且通过隔离彼此分离 所述衬底包括在所述第一晶体管下方的第一掺杂类型的阱，所述阱的第一掺杂类型电连接到所述第一晶体管的源极区，并且在所述第二晶体管的下方包括电连接到所述第二晶体管的源极区的第二掺杂型阱， 从而在第一和第二晶体管的源极之间的衬底中形成结二极管。