公开(公告)号：US11205716B2

公开(公告)日：2021-12-21

申请号：US16662671

申请日：2019-10-24

Applicant: IMEC VZW

Inventor： Veeresh Vidyadhar Deshpande ,  Bertrand Parvais

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/267 ,  H01L29/66

Abstract: A method for forming a heterojunction bipolar transistor is provided. The method includes (a) forming a doped region in a group IV semiconductor layer of a substrate; (b) forming an epitaxially grown III-V semiconductor body on a surface portion of the doped region, the body extending from the surface portion and protruding vertically above the doped region, wherein the doped region and the body forms a first sub-collector part and a second sub-collector part, respectively; and (c) forming an epitaxially grown III-V semiconductor layer stack on the body, the layer stack comprising a collector, a base and an emitter. There is further provided a heterojunction bipolar transistor device.