公开(公告)号：US10128958B1

公开(公告)日：2018-11-13

申请号：US15792597

申请日：2017-10-24

Applicant: INPHI CORPORATION

Inventor： Damián A. Morero ,  Mario R. Hueda ,  Oscar E. Agazzi

IPC: H04B10/079 ,  H04B10/61 ,  H04L1/00

Abstract: A method and structure for signal propagation in a coherent optical receiver device. Asynchronous equalization helps to reduce complexity and power dissipation, and also improves the robustness of timing recovery. However, conventional devices using inverse interpolation filters ignore adaptation algorithms. The present invention provides for forward propagation and backward propagation. In the forward case, the filter input signal is forward propagated through a filter to the adaptation engine, while, in the backward case, the error signal is backward propagated through a filter to the asynchronous domain. Using such forward and backward propagation schemes reduces implementation complexity while providing optical device performance.

公开(公告)号：US11424766B1

公开(公告)日：2022-08-23

申请号：US16778918

申请日：2020-01-31

Applicant: INPHI CORPORATION

Inventor： Mario A. Castrillon ,  Damián A. Morero ,  Genaro Bergero ,  Cristian Cavenio ,  Teodoro Goette ,  Martin Asinari ,  Ramiro R. Lopez ,  Mario R. Hueda

IPC: H03M13/37 ,  H03M13/11 ,  H03M13/01 ,  H03M13/00

Abstract: A method and device for energy-efficient decoders. The decoder device can include a plurality of decoder modules configured to process an input data signal having a plurality of forward error correction (FEC) codewords. This plurality of decoder modules can include at least a first decoder followed by a second decoder. The first decoder can be low-power to first eliminate most of the errors of the codewords and the second decoder can be high-performance to correct the remaining errors. Alternatively, the first decoder can be high-performance to correct the codewords until the low-power decoder can correct the remaining errors. A classifier module can be included to determine portions of the codewords to be directed to any one of the plurality of decoder modules. These implementations can be extended to use additional decoders with different decoding algorithms and optimized to maximize decoder performance given a maximum power constraint.