公开(公告)号：US20240211408A1

公开(公告)日：2024-06-27

申请号：US18087887

申请日：2022-12-23

Applicant: INTEL CORPORATION

Inventor： JOYDEEP RAKSHIT ,  ANANT VITHAL NORI ,  SREENIVAS SUBRAMONEY ,  HANNA ALAM ,  JOSEPH NUZMAN

IPC: G06F12/0891 ,  G06F12/1009

CPC classification number: G06F12/0891 ,  G06F12/1009 ,  G06F2212/1016

Abstract: Apparatus and method for probabilistic cacheline replacement for accelerating address translation. For example, one embodiment of a processor comprises: a plurality of cores, each core to process instructions; a cache to be shared by a subset of the plurality of cores, the cache comprising an N-way set associative cache for storing page table entry (PTE) cachelines and non-PTE cachelines; and a cache manager to implement a PTE-aware eviction policy for evicting cachelines from the cache, the PTE-aware eviction policy to cause a reduction of evictions of PTE cachelines during non-PTE cacheline fills.

公开(公告)号：US20190310853A1

公开(公告)日：2019-10-10

申请号：US16024808

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： RAHUL BERA ,  ANANT VITHAL NORI ,  SREENIVAS SUBRAMONEY ,  HONG WANG

IPC: G06F9/38 ,  G06F12/0875

Abstract: An apparatus and method for adaptive spatial accelerated prefetching. For example, one embodiment of an apparatus comprises: execution circuitry to execute instructions and process data; a Level 2 (L2) cache to store at least a portion of the data; and a prefetcher to prefetch data from a memory subsystem to the L2 cache in anticipation of the data being needed by the execution unit to execute one or more of the instructions, the prefetcher comprising a buffer to store one or more prefetched memory pages or portions thereof, and signature data indicating detected patterns of access to the one or more prefetched memory pages; wherein the prefetcher is to prefetch one or more cache lines based on the signature data.