公开(公告)号：US20230205692A1

公开(公告)日：2023-06-29

申请号：US17561571

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： ANANT NORI ,  RAHUL BERA ,  SHANKAR BALACHANDRAN ,  JOYDEEP RAKSHIT ,  Om Ji OMER ,  SREENIVAS SUBRAMONEY ,  AVISHAII ABUHATZERA ,  BELLIAPPA KUTTANNA

IPC: G06F12/0811 ,  G06F9/48 ,  G06F9/30 ,  G06N3/02

CPC classification number: G06F12/0811 ,  G06F9/4881 ,  G06F9/3012 ,  G06N3/02

Abstract: Apparatus and method for leveraging simultaneous multithreading for bulk compute operations. For example, one embodiment of a processor comprises: a plurality of cores including a first core to simultaneously process instructions of a plurality of threads; a cache hierarchy coupled to the first core and the memory, the cache hierarchy comprising a Level 1 (L1) cache, a Level 2 (L2) cache, and a Level 3 (L3) cache; and a plurality of compute units coupled to the first core including a first compute unit associated with the L1 cache, a second compute unit associated with the L2 cache, and a third compute unit associated with the L3 cache, wherein the first core is to offload instructions for execution by the compute units, the first core to offload instructions from a first thread to the first compute unit, instructions from a second thread to the second compute unit, and instructions from a third thread to the third compute unit.

公开(公告)号：US20190310853A1

公开(公告)日：2019-10-10

申请号：US16024808

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： RAHUL BERA ,  ANANT VITHAL NORI ,  SREENIVAS SUBRAMONEY ,  HONG WANG

IPC: G06F9/38 ,  G06F12/0875

Abstract: An apparatus and method for adaptive spatial accelerated prefetching. For example, one embodiment of an apparatus comprises: execution circuitry to execute instructions and process data; a Level 2 (L2) cache to store at least a portion of the data; and a prefetcher to prefetch data from a memory subsystem to the L2 cache in anticipation of the data being needed by the execution unit to execute one or more of the instructions, the prefetcher comprising a buffer to store one or more prefetched memory pages or portions thereof, and signature data indicating detected patterns of access to the one or more prefetched memory pages; wherein the prefetcher is to prefetch one or more cache lines based on the signature data.