公开(公告)号：US20200334016A1

公开(公告)日：2020-10-22

申请号：US16919022

申请日：2020-07-01

Applicant: INTEL CORPORATION

Inventor： Aditya VARMA ,  Michael ESPIG

IPC: G06F7/544 ,  G06F9/30 ,  G06F7/483

Abstract: An apparatus and method for efficiently performing a multiply add or multiply accumulate operation. For example, one embodiment of a processor comprises: a decoder to decode an instruction specifying an operation, the instruction comprising a first operand identifying a multiplier and a second operand identifying a multiplicand; and fused multiply-add (FMA) execution circuitry comprising first multiplication circuitry to perform a multiplication using the multiplicand and multiplier to generate a result for multipliers and multiplicands falling within a first precision range, and second multiplication circuitry to be used instead of the first multiplication circuitry for multipliers and multiplicands falling within a second precision range.