公开(公告)号：US20240211408A1

公开(公告)日：2024-06-27

申请号：US18087887

申请日：2022-12-23

Applicant: INTEL CORPORATION

Inventor： JOYDEEP RAKSHIT ,  ANANT VITHAL NORI ,  SREENIVAS SUBRAMONEY ,  HANNA ALAM ,  JOSEPH NUZMAN

IPC: G06F12/0891 ,  G06F12/1009

CPC classification number: G06F12/0891 ,  G06F12/1009 ,  G06F2212/1016

Abstract: Apparatus and method for probabilistic cacheline replacement for accelerating address translation. For example, one embodiment of a processor comprises: a plurality of cores, each core to process instructions; a cache to be shared by a subset of the plurality of cores, the cache comprising an N-way set associative cache for storing page table entry (PTE) cachelines and non-PTE cachelines; and a cache manager to implement a PTE-aware eviction policy for evicting cachelines from the cache, the PTE-aware eviction policy to cause a reduction of evictions of PTE cachelines during non-PTE cacheline fills.

公开(公告)号：US20220197808A1

公开(公告)日：2022-06-23

申请号：US17130696

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： HANNA ALAM ,  JOSEPH NUZMAN

IPC: G06F12/0862

Abstract: In one embodiment, a processor includes: one or more execution circuits to execute instructions; a stream prediction circuit coupled to the one or more execution circuits, the stream prediction circuit to receive demand requests for information and, based at least in part on the demand requests, generate a page prefetch hint for a first page; and a prefetcher circuit to generate first prefetch requests each for a cache line, the stream prediction circuit decoupled from the prefetcher circuit. Other embodiments are described and claimed.