公开(公告)号：US20220091851A1

公开(公告)日：2022-03-24

申请号：US17029335

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： FANGFEI LIU ,  ALAA ALAMELDEEN ,  ABHISHEK BASAK ,  SCOTT CONSTABLE ,  FRANCIS MCKEEN ,  JOSEPH NUZMAN ,  CARLOS ROZAS ,  THOMAS UNTERLUGGAUER ,  XIANG ZOU

IPC: G06F9/38 ,  G06F9/48 ,  G06F21/54 ,  G06F9/30

Abstract: In one embodiment, a processor includes: a decode circuit to decode a load instruction that is to load an operand to a destination register, the decode circuit to generate at least one fencing micro-operation (μop) associated with the destination register; and a scheduler circuit coupled to the decode circuit. The scheduler circuit is to prevent speculative execution of one or more instructions that consume the operand in response to the at least one fencing μop. Other embodiments are described and claimed.

公开(公告)号：US20190235938A1

公开(公告)日：2019-08-01

申请号：US16259736

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： TOMER STARK ,  RON GABOR ,  JOSEPH NUZMAN

IPC: G06F11/07 ,  G06F12/06 ,  G06F12/14

CPC classification number: G06F11/073 ,  G06F11/0727 ,  G06F12/0623 ,  G06F12/14 ,  G06F2212/1052 ,  G06F2212/657

Abstract: One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.

公开(公告)号：US20210200684A1

公开(公告)日：2021-07-01

申请号：US16728527

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： RON GABOR ,  ENRICO PERLA ,  RAANAN SADE ,  IGOR YANOVER ,  TOMER STARK ,  JOSEPH NUZMAN

IPC: G06F12/0895 ,  G06F12/1081 ,  G06F12/1009 ,  G06F12/0811 ,  G06F12/14 ,  G06F9/30 ,  G06F11/30

Abstract: An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.

公开(公告)号：US20180060049A1

公开(公告)日：2018-03-01

申请号：US15615798

申请日：2017-06-06

Applicant: Intel Corporation

Inventor： DAVID J. SAGER ,  RUCHIRA SASANKA ,  RON GABOR ,  SHLOMO RAIKIN ,  JOSEPH NUZMAN ,  LEEOR PELED ,  JASON A. DOMER ,  HO-SEOP KIM ,  YOUFENG WU ,  KOICHI YAMADA ,  TIN-FOOK NGAI ,  HOWARD H. CHEN ,  JAYARAM BOBBA ,  JEFFREY J. COOK ,  OMAR M. SHAIKH ,  SURESH SRINIVAS

IPC: G06F9/45 ,  G06F11/36 ,  G06F9/38 ,  G06F9/54

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

公开(公告)号：US20240211408A1

公开(公告)日：2024-06-27

申请号：US18087887

申请日：2022-12-23

Applicant: INTEL CORPORATION

Inventor： JOYDEEP RAKSHIT ,  ANANT VITHAL NORI ,  SREENIVAS SUBRAMONEY ,  HANNA ALAM ,  JOSEPH NUZMAN

IPC: G06F12/0891 ,  G06F12/1009

CPC classification number: G06F12/0891 ,  G06F12/1009 ,  G06F2212/1016

Abstract: Apparatus and method for probabilistic cacheline replacement for accelerating address translation. For example, one embodiment of a processor comprises: a plurality of cores, each core to process instructions; a cache to be shared by a subset of the plurality of cores, the cache comprising an N-way set associative cache for storing page table entry (PTE) cachelines and non-PTE cachelines; and a cache manager to implement a PTE-aware eviction policy for evicting cachelines from the cache, the PTE-aware eviction policy to cause a reduction of evictions of PTE cachelines during non-PTE cacheline fills.

公开(公告)号：US20180004445A1

公开(公告)日：2018-01-04

申请号：US15201443

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： TOMER STARK ,  RON GABOR ,  JOSEPH NUZMAN

IPC: G06F3/06 ,  G06F12/14 ,  G06F12/06 ,  G06F11/07

CPC classification number: G06F12/0623 ,  G06F11/0727 ,  G06F11/073 ,  G06F12/14 ,  G06F2212/1052 ,  G06F2212/657

Abstract: One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.

公开(公告)号：US20160110298A1

公开(公告)日：2016-04-21

申请号：US14519648

申请日：2014-10-21

Applicant: Intel Corporation

Inventor： DAVID A. KOUFATY ,  GILBERT NEIGER ,  RAJESH M. SANKARAN ,  ANDREW V. ANDERSON ,  SUBRAMANYA R. DULLOOR ,  WERNER HAAS ,  JOSEPH NUZMAN

IPC: G06F12/14 ,  G06F21/62

CPC classification number: G06F12/1466 ,  G06F21/52 ,  G06F2212/1052

Abstract: A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a storage unit to store a page table entry including one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode, a first permission register including a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode, and a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode.

Abstract translation: 处理系统包括执行任务的处理核心和耦合到核心的存储器管理单元。 存储器管理单元包括：存储单元，用于存储包括存储器帧的一个或多个标识符的页表项，保护密钥和指示一个或多个存储器帧是否可根据用户模式访问的访问模式位，或者根据 管理员模式，包括多个字段的第一允许寄存器，每个字段包括反映用户模式下的一组存储器访问许可的位数，以及存储多个字段的第二许可寄存器，每个字段包括一组 在管理员模式下反映一组内存访问权限的位。

公开(公告)号：US20230350687A1

公开(公告)日：2023-11-02

申请号：US18143513

申请日：2023-05-04

Applicant: Intel Corporation

Inventor： ROBERT S. CHAPPELL ,  JASON W. BRANDT ,  ALAN COX ,  ASIT MALLICK ,  JOSEPH NUZMAN ,  ARJAN VAN DE VEN

IPC: G06F9/38 ,  G06F9/30 ,  G06F21/55

CPC classification number: G06F9/3842 ,  G06F9/30145 ,  G06F21/556 ,  G06F9/30058 ,  G06F2221/033

Abstract: Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.

公开(公告)号：US20220197808A1

公开(公告)日：2022-06-23

申请号：US17130696

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： HANNA ALAM ,  JOSEPH NUZMAN

IPC: G06F12/0862

Abstract: In one embodiment, a processor includes: one or more execution circuits to execute instructions; a stream prediction circuit coupled to the one or more execution circuits, the stream prediction circuit to receive demand requests for information and, based at least in part on the demand requests, generate a page prefetch hint for a first page; and a prefetcher circuit to generate first prefetch requests each for a cache line, the stream prediction circuit decoupled from the prefetcher circuit. Other embodiments are described and claimed.

公开(公告)号：US20190324756A1

公开(公告)日：2019-10-24

申请号：US16236049

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： ROBERT S. CHAPPELL ,  JASON W. BRANDT ,  ALAN COX ,  ASIT MALLICK ,  JOSEPH NUZMAN ,  ARJAN VAN DE VEN

IPC: G06F9/38 ,  G06F9/30 ,  G06F21/55

Abstract: Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.