公开(公告)号：US20230060900A1

公开(公告)日：2023-03-02

申请号：US17959872

申请日：2022-10-04

Applicant: INTEL CORPORATION

Inventor： Christopher J. HUGHES ,  Jonathan D. PEARCE ,  Guei-Yuan LUEH ,  ElMoustapha OULD-AHMED-VALL ,  Jorge E. PARRA ,  Prasoonkumar SURTI ,  Krishna N. VINOD ,  Ronen ZOHAR

IPC: G06F9/30

Abstract: Embodiments detailed herein relate to reduction operations on a plurality of data element values. In one embodiment, a process comprises decoding circuitry to decode an instruction and execution circuitry to execute the decoded instruction. The instruction specifies a first input register containing a plurality of data element values, a first index register containing a plurality of indices, and an output register, where each index of the plurality of indices maps to one unique data element position of the first input register. The execution includes to identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register.

公开(公告)号：US20220229661A1

公开(公告)日：2022-07-21

申请号：US17712966

申请日：2022-04-04

Applicant: INTEL CORPORATION

Inventor： Christopher J. HUGHES ,  Jonathan D. PEARCE ,  Guei-Yuan LUEH ,  ElMoustapha OULD-AHMED-VALL ,  Jorge E. PARRA ,  Prasoonkumar SURTI ,  Krishna N. VINOD ,  Ronen ZOHAR

IPC: G06F9/30

Abstract: Embodiments detailed herein relate to reduction operations on a plurality of data element values. In one embodiment, a process comprises decoding circuitry to decode an instruction and execution circuitry to execute the decoded instruction. The instruction specifies a first input register containing a plurality of data element values, a first index register containing a plurality of indices, and an output register, where each index of the plurality of indices maps to one unique data element position of the first input register. The execution includes to identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register.

公开(公告)号：US20200310809A1

公开(公告)日：2020-10-01

申请号：US16366155

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  Jonathan D. PEARCE ,  Guei-Yuan LUEH ,  ElMoustapha OULD-AHMED-VALL ,  Jorge E. PARRA ,  Prasoonkumar SURTI ,  Krishna N. VINOD ,  Ronen ZOHAR

IPC: G06F9/30

Abstract: Embodiments detailed herein relate to reduction operations on a plurality of data element values. In one embodiment, a process comprises decoding circuitry to decode an instruction and execution circuitry to execute the decoded instruction. The instruction specifies a first input register containing a plurality of data element values, a first index register containing a plurality of indices, and an output register, where each index of the plurality of indices maps to one unique data element position of the first input register. The execution includes to identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register.

公开(公告)号：US20200310804A1

公开(公告)日：2020-10-01

申请号：US16370922

申请日：2019-03-30

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  ElMoustapha OULD-AHMED-VALL ,  Jorge E. PARRA ,  Prasoonkumar SURTI ,  Krishna N. VINOD ,  Ronen ZOHAR

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38

Abstract: Methods and apparatus for vector-matrix comparison are disclosed. In one embodiment, a processor comprises decoding and execution circuitry. The decoding circuitry decodes an instruction, where operands of the instruction specifies an output location to store output results, a vector of data element values, and a matrix of data element values. The execution circuitry executes the decoded instruction. The execution includes to map each of the data element values of the vector to one of consecutive rows of the matrix; for each data element value of the vector, to compare that data element value of the vector with data element values in a respective row of the matrix and obtain data element match results. The execution further includes to store the output results based on the data element match results, where each output result maps to a respective data element column position and indicates a vector match result.