公开(公告)号：US20230420360A1

公开(公告)日：2023-12-28

申请号：US17850779

申请日：2022-06-27

Applicant: INTEL CORPORATION

Inventor： Mohit HARAN ,  Sukru YEMENICIOGLU ,  Pratik PATEL ,  Charles H. WALLACE ,  Leonard P. GULER ,  Conor P. PULS ,  Makram ABD EL QADER ,  Tahir GHANI

IPC: H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

CPC classification number: H01L23/5226 ,  H01L27/0207 ,  H01L2027/11875 ,  H01L27/11807 ,  H01L23/5283

Abstract: Integrated circuit structures having recessed self-aligned deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.