公开(公告)号：US20230290844A1

公开(公告)日：2023-09-14

申请号：US17694163

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mauro J. KOBRINSKY ,  Ehren MANNEBACH ,  Makram ABD EL QADER ,  Tahir GHANI

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/41783 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/0673 ,  H01L21/823475 ,  H01L29/66439

Abstract: Integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and extends into the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.

公开(公告)号：US20230420360A1

公开(公告)日：2023-12-28

申请号：US17850779

申请日：2022-06-27

Applicant: INTEL CORPORATION

Inventor： Mohit HARAN ,  Sukru YEMENICIOGLU ,  Pratik PATEL ,  Charles H. WALLACE ,  Leonard P. GULER ,  Conor P. PULS ,  Makram ABD EL QADER ,  Tahir GHANI

IPC: H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

CPC classification number: H01L23/5226 ,  H01L27/0207 ,  H01L2027/11875 ,  H01L27/11807 ,  H01L23/5283

Abstract: Integrated circuit structures having recessed self-aligned deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

公开(公告)号：US20220399373A1

公开(公告)日：2022-12-15

申请号：US17348000

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Chanaka MUNASINGHE ,  Makram ABD EL QADER ,  Marie CONTE ,  Saurabh MORARKA ,  Elliot N. TAN ,  Krishna GANESAN ,  Mohit K. HARAN ,  Charles H. WALLACE ,  Tahir GHANI ,  Sean PURSEL

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/84

Abstract: An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.

公开(公告)号：US20240429294A1

公开(公告)日：2024-12-26

申请号：US18212824

申请日：2023-06-22

Applicant: Intel Corporation

Inventor： Shaun MILLS ,  Makram ABD EL QADER ,  Ehren MANNEBACH

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

Abstract: Integrated circuit structures having backside plug last approach are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. A conductive trench contact structure is at a level below the plurality of horizontally stacked nanowires or the fin, the conductive trench contact structure having outwardly tapered sidewalls from a top of the conductive trench contact structure to a bottom of the conductive trench contact structure.

公开(公告)号：US20230317595A1

公开(公告)日：2023-10-05

申请号：US17710817

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Makram ABD EL QADER ,  Tahir GHANI ,  Chanaka D. MUNASINGHE

IPC: H01L23/522 ,  H01L29/06 ,  H01L27/088 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L29/0673 ,  H01L27/0886 ,  H01L23/5283

Abstract: Integrated circuit structures having pre-epitaxial deep via structures, and methods of fabricating integrated circuit structures having pre-epitaxial deep via structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. A conductive via is vertically beneath and extends to the conductive trench contact structure. The conductive via has an uppermost surface above an uppermost surface of the epitaxial source or drain structure.

公开(公告)号：US20240332166A1

公开(公告)日：2024-10-03

申请号：US18129873

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Seda CEKLI ,  Sudipto NASKAR ,  Ananya DUTTA ,  Supanee SUKRITTANON ,  Akshit PEER ,  Navneethakrishnan SALIVATI ,  Jeffery BIELEFELD ,  Makram ABD EL QADER ,  Mauro J. KOBRINSKY ,  Sachin VAIDYA

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53295

Abstract: Integrated circuit structures having air gaps are described. In an example, an integrated circuit structure includes alternating conductive lines and air gaps above a first dielectric layer. A dielectric structure is between adjacent ones of the conductive lines and over the air gaps. A first etch stop layer is on the dielectric structure but not on the conductive lines. A second etch stop layer is on the first etch stop layer and on the conductive lines. A second dielectric layer is above the second etch stop layer. A conductive via structure is in the second dielectric layer, in the second etch stop layer, and on one of the conductive lines.

公开(公告)号：US20230307514A1

公开(公告)日：2023-09-28

申请号：US17706218

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Joseph D'SILVA ,  Mauro J. KOBRINSKY ,  Shaun MILLS ,  Nafees A. KABIR ,  Makram ABD EL QADER ,  Leonard P. GULER

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/66742

Abstract: Gate-all-around integrated circuit structures having backside contact with enhanced area relative to an epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures. The conductive structure is along an entirety of a bottom of the one of the first epitaxial source or drain structures, and the conductive structure can also be along a portion of sides of one of the first epitaxial source or drain structures.

公开(公告)号：US20230197722A1

公开(公告)日：2023-06-22

申请号：US17558026

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Mohammad HASAN ,  Mohit K. HARAN ,  Leonard P. GULER ,  Pratik PATEL ,  Tahir GHANI ,  Anand S. MURTHY ,  Makram ABD EL QADER

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66439

Abstract: Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures. The intervening dielectric structure has a top surface co-planar with a top surface of the gate structure.