公开(公告)号：US10719355B2

公开(公告)日：2020-07-21

申请号：US15890984

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Pooja Roy ,  Jayesh Gaur ,  Sreenivas Subramoney ,  Zeev Sperber ,  Alexandr Titov ,  Lihu Rappoport ,  Stanislav Shwartsman ,  Hong Wang ,  Adi Yoaz ,  Ronak Singhal ,  Robert S. Chappell

IPC: G06F9/48 ,  G06F9/38

Abstract: A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.

公开(公告)号：US20180232235A1

公开(公告)日：2018-08-16

申请号：US15433674

申请日：2017-02-15

Applicant: INTEL CORPORATION

Inventor： Jayesh Gaur ,  Pooja Roy ,  Sreenivas Subramoney ,  Hong Wang ,  Ronak Singhal

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3838 ,  G06F8/41

Abstract: A processor includes a memory to hold a buffer to store data dependencies comprising nodes and edges for each of a plurality of micro-operations. The nodes include a first node for dispatch, a second node for execution, and a third node for commit. A detector circuit is to queue, in the buffer, the nodes of a micro-operation; add, to determine a node weight for each of the nodes of the micro-operation, an edge weight to a previous node weight of a connected micro-operation that yields a maximum node weight for the node, wherein the node weight comprises a number of execution cycles of an OOO pipeline of the processor and the edge weight comprises a number of execution cycles to execute the connected micro-operation; and identify, as a critical path, a path through the data dependencies that yields the maximum node weight for the micro-operation.

公开(公告)号：US20190243684A1

公开(公告)日：2019-08-08

申请号：US15890984

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Pooja Roy ,  Jayesh Gaur ,  Sreenivas Subramoney ,  Zeev Sperber ,  Alexandr Titov ,  Lihu Rappoport ,  Stanislav Shwartsman ,  Hong Wang ,  Adi Yoaz ,  Ronak Singhal ,  Robert S. Chappell

IPC: G06F9/48 ,  G06F9/38

Abstract: A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.