公开(公告)号：US10534613B2

公开(公告)日：2020-01-14

申请号：US15581791

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Gokce Keskin ,  Stephen J. Tarsa ,  Gautham N. Chinya ,  Tsung-Han Lin ,  Perry H. Wang ,  Hong Wang

IPC: G06F9/38 ,  G06N3/08

Abstract: Implementations of the disclosure provide a processing device comprising a branch predictor circuit to obtain a branch history for an application. The branch history comprising references to branching instructions associated with the application and an outcome of executing each branch. Using the branch history, a neutral network is trained to produce a weighted value for each branch of the branching instructions. Features of the branching instructions are identified based on the weighted values. Each feature identifying predictive information regarding the outcome of at least one branch of correlated branches having corresponding outcomes. A feature vector is determined based on the features. The feature vector comprises a plurality of data fields that identify an occurrence of a corresponding feature of the correlated branches with respect to the branch history. Using the feature vector, a data model is produced to determine a predicted outcome associated with the correlated branches.

公开(公告)号：US10452403B2

公开(公告)日：2019-10-22

申请号：US14866875

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Hong Wang ,  John P. Shen ,  Edward T. Grochowski ,  Richard A. Hankins ,  Gautham N. Chinya ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju V. Patel ,  James P Held

IPC: G06F9/455 ,  G06F9/38 ,  G06F9/30 ,  G06F9/48

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

公开(公告)号：US20190286567A1

公开(公告)日：2019-09-19

申请号：US15923174

申请日：2018-03-16

Applicant: Intel Corporation

Inventor： Mainak Chaudhuri ,  Jayesh Gaur ,  Sreenivas Subramoney ,  Hong Wang

IPC: G06F12/0895 ,  G06F12/0891 ,  G06F12/0804 ,  G06F12/12

Abstract: In one embodiment, a processor includes: a cache memory to store a plurality of cache lines; and a cache controller to control the cache memory. The cache controller may include a control circuit to allocate a virtual write buffer within the cache memory in response to a bandwidth on an interconnect that exceeds a first bandwidth threshold. The cache controller may further include a replacement circuit to control eviction of cache lines from the cache memory. Other embodiments are described and claimed.

公开(公告)号：US20180349144A1

公开(公告)日：2018-12-06

申请号：US15614757

申请日：2017-06-06

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Ragavendra Natarajan ,  Niranjan K. Soundararajan ,  Sreenivas Subramoney ,  Daniel Deng ,  Jared Warner Stark, IV ,  Hong Wang ,  Ronak Singhal

IPC: G06F9/38

Abstract: In one embodiment, a processor comprises a branch predictor to generate, in association with a program loop, a frozen history vector comprising a snapshot of a branch history vector; track a current iteration of the program loop; and provide a prediction for a branch instruction associated with the program loop, the prediction based on the frozen history vector and the current iteration of the program loop.

公开(公告)号：US20180314524A1

公开(公告)日：2018-11-01

申请号：US15581791

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Gokce Keskin ,  Stephen J. Tarsa ,  Gautham N. Chinya ,  Tsung-Han Lin ,  Perry H. Wang ,  Hong Wang

IPC: G06F9/38 ,  G06N3/08

Abstract: Implementations of the disclosure provide a processing device comprising a branch predictor circuit to obtain a branch history for an application. The branch history comprising references to branching instructions associated with the application and an outcome of executing each branch. Using the branch history, a neutral network is trained to produce a weighted value for each branch of the branching instructions. Features of the branching instructions are identified based on the weighted values. Each feature identifying predictive information regarding the outcome of at least one branch of correlated branches having corresponding outcomes. A feature vector is determined based on the features. The feature vector comprises a plurality of data fields that identify an occurrence of a corresponding feature of the correlated branches with respect to the branch history. Using the feature vector, a data model is produced to determine a predicted outcome associated with the correlated branches.

公开(公告)号：US20180285115A1

公开(公告)日：2018-10-04

申请号：US15477064

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Niranjan K. Soundararajan ,  Saurabh Gupta ,  Sreenivas Subramoney ,  Rahul Pal ,  Ragavendra Natarajan ,  Daniel Deng ,  Jared W. Stark ,  Ronak Singhal ,  Hong Wang

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/46

CPC classification number: G06F9/46 ,  G06F9/3848

Abstract: Embodiments of apparatuses, methods, and systems for misprediction-triggered local history-based branch prediction are described. In one embodiments, an apparatus includes a current pattern table and a local pattern table. The current pattern table has a plurality of entries, each entry in which to store a plurality of pattern lengths of a current pattern of one of a plurality of branch instructions. The local pattern table is to provide a first branch prediction based on the current pattern.

公开(公告)号：US10089263B2

公开(公告)日：2018-10-02

申请号：US15118501

申请日：2014-03-24

Applicant: INTEL CORPORATION ,  Thiam Wah Loh ,  Gautham N. Chinya ,  Per Hammarlund ,  Reza Fortas ,  Hong Wang ,  Huajin Sun

Inventor： Thiam Wah Loh ,  Gautham N. Chinya ,  Per Hammarlund ,  Reza Fortas ,  Hong Wang ,  Huajin Sun

IPC: G06F13/24

Abstract: A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.

公开(公告)号：US09910796B2

公开(公告)日：2018-03-06

申请号：US13844343

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Hong Wang ,  Per Hammarlund ,  Xiang Zou ,  John P. Shen ,  Xinmin Tian ,  Milind Girkar ,  Perry H. Wang ,  Piyush N. Desai

IPC: G06F9/38 ,  G06F13/24 ,  G06F9/30 ,  G06F9/48 ,  G06F11/34

CPC classification number: G06F13/24 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  G06F11/3024 ,  G06F11/348 ,  G06F12/0875 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/452

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

公开(公告)号：US09588771B2

公开(公告)日：2017-03-07

申请号：US13791298

申请日：2013-03-08

Applicant: Intel Corporation

Inventor： Hong Wang ,  John Shen ,  Hong Jiang ,  Richard Hankins ,  Per Hammarlund ,  Dion Rodgers ,  Gautham Chinya ,  Baiju Patel ,  Shiv Kaushik ,  Bryant Bigbee ,  Gad Sheaffer ,  Yoav Talgam ,  Yuval Yosef ,  James P. Held

IPC: G06F9/38 ,  G06F9/30 ,  G06T1/20

CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在加速器和与其耦合的指令定序器之间直接通信的方法，其中加速器相对于指令定序器是异质资源。 可以使用接口来提供这些资源之间的通信。 通过这种通信机制，用户级应用可以直接与加速器进行通信，而无需操作系统支持。 此外，指令定序器和加速器可以并行地执行操作。 描述和要求保护其他实施例。

公开(公告)号：US09003164B2

公开(公告)日：2015-04-07

申请号：US14221741

申请日：2014-03-21

Applicant: Intel Corporation

Inventor： Gautham N. Chinya ,  Hong Wang ,  Deepak A. Mathaikutty ,  Jamison D. Collins ,  Ethan Schuchman ,  James P. Held ,  Ajay V. Bhatt ,  Prashant Sethi ,  Stephen F. Whalley

IPC: G06F12/10 ,  G06F12/12

CPC classification number: G06F12/1036 ,  G06F12/1027 ,  G06F12/121 ,  G06F2212/254

Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有存储虚拟地址到物理地址转换的条目的存储器管理单元（MMU），其中每个条目包括位置指示符，以指示相应条目的存储器位置是否存在于本地或远程 记忆。 以这种方式，可以在两个存储器之间共享公共虚拟存储器空间，这两个存储器可以由一个或多个非相干链路分隔。 描述和要求保护其他实施例。